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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2017-12-22
- Size : 1kb
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- Author ：哈*****
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Introduction - If you have any usage issues, please Google them yourself
Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.
Packet file list
(Preview for download)
| Filename | Size | Update |
|---|---|---|
| 计算器.txt | 15903 | 2017-12-22 |
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