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Category :
VHDL-FPGA-Verilog
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Update : 2017-12-26
Size : 134kb
Downloaded :0次
Author :
liujhl*******
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
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Digital clock, designed in VHDL language, can adjust the time, the whole bell ring
Packet file list
(Preview for download)
Filename
Size
Update
clock\cclock.vhd
1090
2017-06-17
clock\clk_ring.qpf
1262
2017-06-16
clock\clk_ring.qsf
3006
2017-06-17
clock\clk_ring.qws
2552
2017-06-17
clock\clk_ring.vhd
537
2007-07-05
clock\clk_ring.vhd.bak
532
2017-06-16
clock\cnt24.vhd
771
2017-06-17
clock\cnt24.vhd.bak
782
2017-06-17
clock\cnt60.vhd
719
2007-06-28
clock\cnt60.vhd.bak
746
2017-06-16
clock\db\add_sub_0ih.tdf
2430
2017-06-17
clock\db\clk_ring.db_info
137
2017-06-17
clock\db\clk_ring.eco.cdb
161
2017-06-17
clock\db\clk_ring.sld_design_entry.sci
154
2017-06-17
clock\db\digitclk.db_info
137
2017-06-28
clock\db\digitclk.eco.cdb
161
2017-06-28
clock\db\digitclk.sim.cvwf
1785
2017-06-17
clock\db\digitclk.sld_design_entry.sci
154
2017-06-28
clock\db\prev_cmp_digitclk.asm.qmsg
1996
2017-06-17
clock\db\prev_cmp_digitclk.fit.qmsg
6166
2017-06-17
clock\db\prev_cmp_digitclk.map.qmsg
20714
2017-06-17
clock\db\prev_cmp_digitclk.qmsg
183185
2017-06-17
clock\db\prev_cmp_digitclk.sim.qmsg
3308
2017-06-17
clock\db\prev_cmp_digitclk.tan.qmsg
154080
2017-06-17
clock\db\wed.wsf
14172
2017-06-17
clock\digitclk.asm.rpt
7763
2017-06-17
clock\digitclk.done
26
2017-06-17
clock\digitclk.dpf
239
2017-06-17
clock\digitclk.fit.rpt
48763
2017-06-17
clock\digitclk.fit.summary
373
2017-06-17
clock\digitclk.flow.rpt
7356
2017-06-17
clock\digitclk.map.rpt
46671
2017-06-17
clock\digitclk.map.summary
292
2017-06-17
clock\digitclk.pin
18525
2017-06-17
clock\digitclk.pof
212109
2017-06-17
clock\digitclk.qpf
908
2017-06-17
clock\digitclk.qsf
3620
2017-06-28
clock\digitclk.qws
534
2017-06-28
clock\digitclk.sim.rpt
44708
2017-06-17
clock\digitclk.sof
57967
2017-06-17
clock\digitclk.tan.rpt
400682
2017-06-17
clock\digitclk.tan.summary
3379
2017-06-17
clock\digitclk.vhd
1889
2017-06-17
clock\digitclk.vhd.bak
1886
2017-06-17
clock\digitclk.vwf
16062
2017-06-17
clock\digitclk_assignment_defaults.qdf
42468
2017-06-28
clock\encode14.vhd
529
2007-06-28
clock\incremental_db\compiled_partitions\digitclk.root_partition.map.kpt
342
2017-06-17
clock\incremental_db\README
653
2017-06-17
clock\pin.png
21467
2017-06-17
clock\ring.vhd
725
2007-06-29
clock\ring.vhd.bak
699
2017-06-16
clock\sorce.png
7363
2017-06-17
clock\timing.png
3953
2017-06-17
clock\wave.png
27042
2017-06-17
clock\incremental_db\compiled_partitions
clock\db
clock\incremental_db
clock
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