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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-12-26
  • Size : 4kb
  • Downloaded :0次
  • Author :小****
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Introduction - If you have any usage issues, please Google them yourself
Test the FPGA filter passed on vivado
Packet file list
(Preview for download)
FilenameSizeUpdate
lab4
lab4\FIR_count.v 303 2016-11-15
lab4\FIR_filter.v 1784 2016-11-15
lab4\FIR_top.v 411 2016-11-15
lab4\Matlab
lab4\Matlab\mylowerfilter.m 629 2016-11-15
lab4\Matlab\result.m 151 2016-11-15
lab4\Matlab\signal.m 325 2016-11-15
lab4\coe
lab4\coe\filter_data.coe 4464 2016-11-15
lab4\multip.v 940 2016-11-15
lab4\sim
lab4\sim\FIR_tb.v 252 2016-11-15
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