A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data Data (from left to right). When the sequence is detected, the output Out is 1. When the sequence is not detected, the output Out is 0. (1) design by state machine method; (2) design with Verilog HDL language and use Modelsim software to do functional simulation.

Filename	Size	Update
lab1.v	919	2017-11-20
lab1.v.bak	926	2017-11-20
lab1_tb.v	239	2017-11-20
lab1_tb.v.bak	239	2017-11-20

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