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basic verilog codes

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-01-10
  • Size : 9.17kb
  • Downloaded :0次
  • Author :spgp1306
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Introduction - If you have any usage issues, please Google them yourself
Basic Verilog code includes RING and Johnson counters, Up-down counters, RAM, ROM, SIPO, PISO, SISO, PIPO, Mealy and Moo
Packet file list
(Preview for download)
Packet : basic_codes.rar filelist
d_negedge.v
upcounter_asyn_load.v
unsigned_downcounter.v
test_moore_101.v
test_mealy_101.v
siso.v
sipo.v
single_port_RAM.v
rom.v
ripple_adder.v
ring_counter.v
priority_encoder.v
piso.v
pipo.v
moore_101.v
mod10_counter.v
mealy_101.v
logical_shifter.v
johnson_counter.v
dual_port_ram_with_en.v
decoder3_8.v
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