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VGA_display_picture

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-01-23
  • Size : 18.45mb
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  • Author :布*****
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Introduction - If you have any usage issues, please Google them yourself
Realization of image processing based on FPGA
Packet file list
(Preview for download)
FilenameSizeUpdate
VGA_display_picture 0 2017-08-20
VGA_display_picture\.Xil 0 2017-07-12
VGA_display_picture\.Xil\Canny_edge_detection_propImpl.xdc 422 2017-07-11
VGA_display_picture\.Xil\VGA_display_picture_propImpl.xdc 423 2017-07-12
VGA_display_picture\VGA_display_picture.cache 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\compile_simlib 0 2017-07-11
VGA_display_picture\VGA_display_picture.cache\compile_simlib\activehdl 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\compile_simlib\ies 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\compile_simlib\modelsim 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\compile_simlib\questa 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\compile_simlib\riviera 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\compile_simlib\vcs 0 2017-08-20
VGA_display_picture\VGA_display_picture.cache\wt 0 2017-07-12
VGA_display_picture\VGA_display_picture.cache\wt\java_command_handlers.wdf 543 2017-08-20
VGA_display_picture\VGA_display_picture.cache\wt\project.wpc 62 2017-08-20
VGA_display_picture\VGA_display_picture.cache\wt\synthesis.wdf 3766 2017-08-20
VGA_display_picture\VGA_display_picture.cache\wt\synthesis_details.wdf 100 2017-08-20
VGA_display_picture\VGA_display_picture.cache\wt\webtalk_pa.xml 1610 2017-08-20
VGA_display_picture\VGA_display_picture.cache\wt\xsim.wdf 239 2017-07-12
VGA_display_picture\VGA_display_picture.hw 0 2017-08-20
VGA_display_picture\VGA_display_picture.hw\VGA_display_picture.lpr 343 2017-07-11
VGA_display_picture\VGA_display_picture.hw\hw_1 0 2017-07-11
VGA_display_picture\VGA_display_picture.hw\hw_1\hw.xml 852 2017-08-20
VGA_display_picture\VGA_display_picture.hw\hw_1\layout 0 2017-07-11
VGA_display_picture\VGA_display_picture.hw\hw_1\layout\dashboard_1.layout 232875 2017-07-11
VGA_display_picture\VGA_display_picture.hw\hw_1\wave 0 2017-08-20
VGA_display_picture\VGA_display_picture.hw\webtalk 0 2017-08-20
VGA_display_picture\VGA_display_picture.hw\webtalk\.xsim_webtallk.info 60 2017-08-20
VGA_display_picture\VGA_display_picture.hw\webtalk\labtool_webtalk.log 922 2017-08-20
VGA_display_picture\VGA_display_picture.hw\webtalk\usage_statistics_ext_labtool.html 2878 2017-08-20
VGA_display_picture\VGA_display_picture.hw\webtalk\usage_statistics_ext_labtool.xml 2444 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\README.txt 130 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\ip 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\ip\clk_VGA 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\ip\clk_VGA\clk_VGA.veo 3587 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\ip\clk_VGA\clk_VGA_stub.v 1189 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ip\clk_VGA\clk_VGA_stub.vhdl 1159 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ip\rom_pic 0 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ip\rom_pic\rom_pic.veo 2967 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ip\rom_pic\rom_pic.vho 3204 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ip\rom_pic\rom_pic_stub.v 1266 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ip\rom_pic\rom_pic_stub.vhdl 1333 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\ipstatic 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\ipstatic\blk_mem_gen_v8_3_1 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\ipstatic\blk_mem_gen_v8_3_1\simulation 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\ipstatic\blk_mem_gen_v8_3_1\simulation\blk_mem_gen_v8_3.vhd 222214 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\mem_init_files 0 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\mem_init_files\200x200.coe 240169 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\mem_init_files\200x200RGB565.coe 200064 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\mem_init_files\lena.coe 240169 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\mem_init_files\rom_pic.mif 680000 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\mem_init_files\summary.log 906 2017-08-20
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA 0 2017-07-11
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\README.txt 3236 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\README.txt 2468 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\clk_VGA.sh 6987 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\file_info.txt 520 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\filelist.f 154 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\filelist_irun.f 250 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\glbl.v 1470 2015-11-18
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\ies\simulate.do 158 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\README.txt 2468 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\clk_VGA.sh 5559 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\clk_VGA.udo 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\compile.do 330 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\file_info.txt 520 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\filelist.f 154 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\glbl.v 1470 2015-11-18
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\simulate.do 300 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\modelsim\wave.do 32 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\README.txt 2468 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\clk_VGA.sh 5676 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\clk_VGA.udo 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\compile.do 324 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\elaborate.do 172 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\file_info.txt 520 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\filelist.f 154 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\glbl.v 1470 2015-11-18
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\simulate.do 191 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\questa\wave.do 32 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs\README.txt 2468 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs\clk_VGA.sh 6915 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs\file_info.txt 520 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs\filelist.f 154 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs\glbl.v 1470 2015-11-18
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\vcs\simulate.do 11 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim 0 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\README.txt 2468 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\clk_VGA.sh 4712 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\cmd.tcl 464 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\file_info.txt 520 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\filelist.f 154 2017-07-12
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\glbl.v 1470 2015-11-18
VGA_display_picture\VGA_display_picture.ip_user_files\sim_scripts\clk_VGA\xsim\vlog.prj 243 2017-07-12
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