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verilog add4

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-01-25
  • Size : 500kb
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  • Author :yz***
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Introduction - If you have any usage issues, please Google them yourself
Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.
Packet file list
(Preview for download)
FilenameSizeUpdate
add4\parta 0 2017-05-17
add4\parta\add4.v 276 2015-06-15
add4\parta\add8.v 359 2015-06-15
add4\parta\addertb.v 764 2017-04-11
add4\parta\cm.log 2391 2017-05-02
add4\parta\compiler.log 2129 2017-05-02
add4\parta\csrc 0 2017-05-02
add4\parta\csrc\_vcsobj_1_1.a 74520 2017-05-02
add4\parta\csrc\_vcsobj_1_1.a.info 22 2017-05-02
add4\parta\csrc\_vcsobj_archive_info_0.lst 19 2017-05-02
add4\parta\csrc\5NrI_d.o 3524 2017-05-02
add4\parta\csrc\5NrIB_d.o 53950 2017-05-02
add4\parta\csrc\filelist 845 2017-05-02
add4\parta\csrc\filelist.dpi 0 2017-05-02
add4\parta\csrc\filelist.hsopt 216 2017-05-02
add4\parta\csrc\hsim 0 2017-05-02
add4\parta\csrc\incr_fileindex.db 1004 2017-05-02
add4\parta\csrc\incr_filename.db 46 2017-05-02
add4\parta\csrc\incr_filenode.db 144 2017-05-02
add4\parta\csrc\incr_filespace.db 10453 2017-05-02
add4\parta\csrc\Makefile 2779 2017-05-02
add4\parta\csrc\Makefile.hsopt 884 2017-05-02
add4\parta\csrc\product_timestamp 0 2017-05-02
add4\parta\csrc\rmapats.c 321 2017-05-02
add4\parta\csrc\rmapats.h 26311 2017-05-02
add4\parta\csrc\rmapats.m 5194 2017-05-02
add4\parta\csrc\rmapats.o 779 2017-05-02
add4\parta\csrc\rmapats_mop.o 958 2017-05-02
add4\parta\csrc\SIM_l.o 333 2017-05-02
add4\parta\csrc\vcsconst.incr 530 2017-05-02
add4\parta\csrc\vcspieces.incr 17 2017-05-02
add4\parta\csrc\vcstype.incr 500 2017-05-02
add4\parta\default.svf 8960 2017-04-12
add4\parta\DVEfiles 0 2017-05-02
add4\parta\DVEfiles\dve_gui.log 50 2017-05-02
add4\parta\DVEfiles\dve_history.log 11942 2017-05-02
add4\parta\DVEfiles\dve_qtwarnings.log 0 2017-05-02
add4\parta\DVEfiles\session.tcl 10615 2017-05-02
add4\parta\DVEfiles\session_2017-05-02T15^%25^%03.tcl 12343 2017-05-02
add4\parta\DVEfiles\session_2017-05-02T15^%33^%56.tcl 12285 2017-05-02
add4\parta\fa.v 112 2015-06-15
add4\parta\file_list.f 63 2017-04-24
add4\parta\makefile 553 2017-05-02
add4\parta\makefile~ 299 2017-04-09
add4\parta\simv_addr 778976 2017-05-02
add4\parta\simv_addr.daidir 0 2017-05-02
add4\parta\simv_addr.daidir\.vcs.timestamp 3099 2017-05-02
add4\parta\simv_addr.daidir\.version 102 2017-05-02
add4\parta\simv_addr.daidir\adhsoptmap.dat 8 2017-05-02
add4\parta\simv_addr.daidir\AllModulesSkeletons.db 744 2017-05-02
add4\parta\simv_addr.daidir\build_db 416 2017-05-02
add4\parta\simv_addr.daidir\compat.db 989 2017-05-02
add4\parta\simv_addr.daidir\connectivity.db 68 2017-05-02
add4\parta\simv_addr.daidir\connectivitydbg.db 0 2017-05-02
add4\parta\simv_addr.daidir\covg_defs 0 2017-05-02
add4\parta\simv_addr.daidir\didmap.db 1429 2017-05-02
add4\parta\simv_addr.daidir\dumpcheck.db 0 2017-05-02
add4\parta\simv_addr.daidir\dve_debug.db 2286 2017-05-02
add4\parta\simv_addr.daidir\elabmoddb_fileindex.db 1004 2017-05-02
add4\parta\simv_addr.daidir\elabmoddb_filename.db 188 2017-05-02
add4\parta\simv_addr.daidir\elabmoddb_filenode.db 288 2017-05-02
add4\parta\simv_addr.daidir\elabmoddb_filespace.db 247 2017-05-02
add4\parta\simv_addr.daidir\external_functions 457 2017-05-02
add4\parta\simv_addr.daidir\incr_fileindex.db 1004 2017-05-02
add4\parta\simv_addr.daidir\incr_filename.db 40 2017-05-02
add4\parta\simv_addr.daidir\incr_filenode.db 96 2017-05-02
add4\parta\simv_addr.daidir\incr_filespace.db 114 2017-05-02
add4\parta\simv_addr.daidir\modfilename.db 419 2017-05-02
add4\parta\simv_addr.daidir\nsparam.dat 8 2017-05-02
add4\parta\simv_addr.daidir\offfilename.db 72 2017-05-02
add4\parta\simv_addr.daidir\rmapats.dat 12 2017-05-02
add4\parta\simv_addr.daidir\str.db 3323 2017-05-02
add4\parta\simv_addr.daidir\topmodules 12 2017-05-02
add4\parta\simv_addr.daidir\tt_fileindex.db 1004 2017-05-02
add4\parta\simv_addr.daidir\tt_filename.db 28 2017-05-02
add4\parta\simv_addr.daidir\tt_filenode.db 144 2017-05-02
add4\parta\simv_addr.daidir\tt_filespace.db 26314 2017-05-02
add4\parta\simv_addr.daidir\vcs_rebuild 385 2017-05-02
add4\parta\simv_addr.daidir\vcselab_master_hsim_elabmod_insts.dat 28 2017-05-02
add4\parta\simv_addr.daidir\vcselab_master_hsim_elabout.db 3999 2017-05-02
add4\parta\simv_addr.daidir\vcselab_master_hsim_fs.dat 28 2017-05-02
add4\parta\simv_addr.daidir\vcselab_master_hsim_mimo_tables.dat 8 2017-05-02
add4\parta\simv_addr.daidir\vcselab_master_hsim_tables.dat 12 2017-05-02
add4\parta\simv_addr.daidir\vcselab_master_hsim_vecconst.dat 8 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_hsdef.db 8 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_hsim_elab.db 12514 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_hsim_fegate.db 112 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_hsim_lvl.db 16 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_hsim_merge.db 344 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_mnmn.db 20 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_partition.db 164 2017-05-02
add4\parta\simv_addr.daidir\vcselab_misc_vcselabref.db 1 2017-05-02
add4\parta\simv_addr.daidir\vir_fileindex.db 1004 2017-05-02
add4\parta\simv_addr.daidir\vir_filename.db 193 2017-05-02
add4\parta\simv_addr.daidir\vir_filenode.db 480 2017-05-02
add4\parta\simv_addr.daidir\vir_filespace.db 25246 2017-05-02
add4\parta\simv_addr.daidir\vloganErrorCheck.db 538 2017-05-02
add4\parta\simv_addr.log 1032 2017-05-02
add4\parta\simv_addr.vdb 0 2017-05-02
add4\parta\simv_addr.vdb\.cmoptions 210 2017-05-02
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