Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation platform is based on the VCS of SYNOPSYS tools.

Filename	Size	Update
fifo\.nfs1746	3430	2015-06-15
fifo\cleanup	140	2015-06-15
fifo\fifo.sva	579	2015-06-15
fifo\fifo.v	3051	2015-06-15
fifo\fifo_tb.v	7121	2015-06-15
fifo\run_debug	21	2015-06-15
fifo\run_debug_all	25	2015-06-15
fifo\run_debug_sva	92	2015-06-15
fifo\run1.f	22	2015-06-15
fifo\run1sva.f	36	2015-06-15
fifo\start_over	0	2017-04-06
fifo\start_over\fifo.v	3051	2015-06-15
fifo\start_over\fifo_fix1	3046	2015-06-15
fifo\start_over\fifo_tb.v	7121	2015-06-15
fifo\start_over\run1.f	23	2015-06-15
fifo\vcdplus_trace.vpd	4235	2015-06-15

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