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51CTO下载-VerilogHDL程序设计实例详解12

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-01-27
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Introduction - If you have any usage issues, please Google them yourself
VerilogHDL program design example detailed solution
Packet file list
(Preview for download)
FilenameSizeUpdate
Chapter-12 0 2012-10-22
Chapter-12\ata 0 2012-10-22
Chapter-12\ata\ata.cr.mti 2825 2007-08-23
Chapter-12\ata\ata.mpf 20332 2007-08-23
Chapter-12\ata\ata_device.v 9985 2007-08-20
Chapter-12\ata\atahost_controller.v 3826 2007-08-23
Chapter-12\ata\atahost_pio_tctrl.v 3121 2007-08-23
Chapter-12\ata\atahost_top.v 4658 2007-08-20
Chapter-12\ata\atahost_wb_slave.v 11654 2007-08-23
Chapter-12\ata\chart 0 2012-10-22
Chapter-12\ata\chart\Thumbs.db 30208 2007-08-24
Chapter-12\ata\chart\ͼ12-10.bmp 543174 2007-08-21
Chapter-12\ata\chart\ͼ12-14.bmp 586974 2007-08-21
Chapter-12\ata\chart\ͼ12-15.bmp 586974 2007-08-21
Chapter-12\ata\chart\ͼ12-16.bmp 586974 2007-08-21
Chapter-12\ata\chart\ͼ12-3.bmp 400526 2007-08-21
Chapter-12\ata\chart\ͼ12-4.bmp 549374 2007-08-21
Chapter-12\ata\chart\ͼ12-5.bmp 593674 2007-08-21
Chapter-12\ata\chart\ͼ12-7.bmp 411774 2007-08-21
Chapter-12\ata\chart\ͼ12-8.bmp 455574 2007-08-21
Chapter-12\ata\ro_cnt.v 920 2007-08-23
Chapter-12\ata\test_bench_top.v 19052 2007-08-23
Chapter-12\ata\timescale.v 21 2007-08-23
Chapter-12\ata\transcript 519 2007-12-20
Chapter-12\ata\ud_cnt.v 936 2007-08-23
Chapter-12\ata\vsim.wlf 1490944 2007-08-21
Chapter-12\ata\wave 0 2012-10-22
Chapter-12\ata\wave\Thumbs.db 26112 2007-12-10
Chapter-12\ata\wave\ata_device.bmp 1865766 2007-08-21
Chapter-12\ata\wave\atahost_controller.bmp 2993794 2007-08-21
Chapter-12\ata\wave\atahost_pio_tctrl.bmp 2206490 2007-08-21
Chapter-12\ata\wave\atahost_top.bmp 2606758 2007-08-21
Chapter-12\ata\wave\atahost_wb_slave.bmp 2269342 2007-08-21
Chapter-12\ata\wave\ro_cnt.bmp 1204166 2007-08-21
Chapter-12\ata\wave\test_bench_top.bmp 2293030 2007-08-21
Chapter-12\ata\wb_mast_model.v 6307 2007-08-23
Chapter-12\ata\wb_model_defines.v 21 2007-08-20
Chapter-12\ata\wb_slv_model.v 1810 2007-08-23
Chapter-12\ata\work 0 2012-10-22
Chapter-12\ata\work\_info 2067 2007-08-23
Chapter-12\ata\work\ata_device 0 2012-10-22
Chapter-12\ata\work\ata_device\_primary.dat 5820 2007-08-23
Chapter-12\ata\work\ata_device\_primary.vhd 522 2007-08-23
Chapter-12\ata\work\ata_device\verilog.asm 56561 2007-08-23
Chapter-12\ata\work\atahost_controller 0 2012-10-22
Chapter-12\ata\work\atahost_controller\_primary.dat 3253 2007-08-23
Chapter-12\ata\work\atahost_controller\_primary.vhd 1734 2007-08-23
Chapter-12\ata\work\atahost_controller\verilog.asm 29044 2007-08-23
Chapter-12\ata\work\atahost_pio_tctrl 0 2012-10-22
Chapter-12\ata\work\atahost_pio_tctrl\_primary.dat 2814 2007-08-23
Chapter-12\ata\work\atahost_pio_tctrl\_primary.vhd 1047 2007-08-23
Chapter-12\ata\work\atahost_pio_tctrl\verilog.asm 25248 2007-08-23
Chapter-12\ata\work\atahost_top 0 2012-10-22
Chapter-12\ata\work\atahost_top\_primary.dat 3632 2007-08-23
Chapter-12\ata\work\atahost_top\_primary.vhd 1608 2007-08-23
Chapter-12\ata\work\atahost_top\verilog.asm 23471 2007-08-23
Chapter-12\ata\work\atahost_wb_slave 0 2012-10-22
Chapter-12\ata\work\atahost_wb_slave\_primary.dat 7208 2007-08-23
Chapter-12\ata\work\atahost_wb_slave\_primary.vhd 3409 2007-08-23
Chapter-12\ata\work\atahost_wb_slave\verilog.asm 66369 2007-08-23
Chapter-12\ata\work\ro_cnt 0 2012-10-22
Chapter-12\ata\work\ro_cnt\_primary.dat 819 2007-08-23
Chapter-12\ata\work\ro_cnt\_primary.vhd 545 2007-08-23
Chapter-12\ata\work\ro_cnt\verilog.asm 8851 2007-08-23
Chapter-12\ata\work\ro_cnt1 0 2012-10-22
Chapter-12\ata\work\ro_cnt1\_primary.dat 786 2007-08-20
Chapter-12\ata\work\ro_cnt1\_primary.vhd 571 2007-08-20
Chapter-12\ata\work\ro_cnt1\verilog.asm 7739 2007-08-20
Chapter-12\ata\work\test_bench_top 0 2012-10-22
Chapter-12\ata\work\test_bench_top\_primary.dat 17827 2007-08-23
Chapter-12\ata\work\test_bench_top\_primary.vhd 88 2007-08-23
Chapter-12\ata\work\test_bench_top\verilog.asm 190969 2007-08-23
Chapter-12\ata\work\ud_cnt 0 2012-10-22
Chapter-12\ata\work\ud_cnt\_primary.dat 783 2007-08-23
Chapter-12\ata\work\ud_cnt\_primary.vhd 591 2007-08-23
Chapter-12\ata\work\ud_cnt\verilog.asm 10826 2007-08-23
Chapter-12\ata\work\wb_mast 0 2012-10-22
Chapter-12\ata\work\wb_mast\_primary.dat 7384 2007-08-23
Chapter-12\ata\work\wb_mast\_primary.vhd 747 2007-08-23
Chapter-12\ata\work\wb_mast\verilog.asm 53461 2007-08-23
Chapter-12\ata\work\wb_slv 0 2012-10-22
Chapter-12\ata\work\wb_slv\_primary.dat 2329 2007-08-23
Chapter-12\ata\work\wb_slv\_primary.vhd 743 2007-08-23
Chapter-12\ata\work\wb_slv\verilog.asm 25962 2007-08-23
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