ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */ ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */ | AT91C_DDRC2_TXSNR_(27) /* 19 * 7.5 = 142.5 ns*/ | AT91C_DDRC2_TRFC_(26)); /* 18 * 7.5 = 135 ns */

Filename	Size	Update
MT47H64M16HR.pdf	9508325	2018-01-30
43-46DR82560C-16128C.pdf	1705395	2018-01-30

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