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DE2_70_D5M_LTM

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-01-30
  • Size : 197kb
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  • Author :jor***
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filtre de sobel sur fpga
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DE2_70_D5M_LTM\Sdram_Control_4Port\Sdram_Params.h 1542 2006-01-05
DE2_70_D5M_LTM\V\Line_Buffer.bsf 3157 2008-04-09
DE2_70_D5M_LTM\V\Line_Buffer_dval.bsf 3093 2008-04-12
DE2_70_D5M_LTM\Sdram_Control_4Port\Sdram_PLL.bsf 3943 2007-09-28
DE2_70_D5M_LTM\DE2_70.cdf 339 2008-08-25
DE2_70_D5M_LTM\DE2_70.done 26 2008-09-17
DE2_70_D5M_LTM\DE2_70.pin 104053 2008-09-17
DE2_70_D5M_LTM\DE2_70.pof 2097354 2008-09-17
DE2_70_D5M_LTM\Sdram_Control_4Port\Sdram_PLL.ppf 503 2007-09-28
DE2_70_D5M_LTM\DE2_70_assignment_defaults.qdf 33002 2008-04-10
DE2_70_D5M_LTM\DE2_70.qpf 907 2008-04-09
DE2_70_D5M_LTM\DE2_70.qsf 31030 2008-09-17
DE2_70_D5M_LTM\DE2_70.qws 175 2008-09-17
DE2_70_D5M_LTM\DE2_70.asm.rpt 8219 2008-09-17
DE2_70_D5M_LTM\DE2_70.fit.rpt 682421 2008-09-17
DE2_70_D5M_LTM\DE2_70.flow.rpt 5555 2008-09-17
DE2_70_D5M_LTM\DE2_70.map.rpt 712686 2008-09-17
DE2_70_D5M_LTM\DE2_70.tan.rpt 884641 2008-09-17
DE2_70_D5M_LTM\DE2_70.fit.smsg 513 2008-09-17
DE2_70_D5M_LTM\DE2_70.sof 1768884 2008-09-17
DE2_70_D5M_LTM\DE2_70.fit.summary 621 2008-09-17
DE2_70_D5M_LTM\DE2_70.map.summary 476 2008-09-17
DE2_70_D5M_LTM\DE2_70.tan.summary 5294 2008-09-17
DE2_70_D5M_LTM\V\CCD_Capture.v 4072 2008-05-04
DE2_70_D5M_LTM\Sdram_Control_4Port\command.v 18879 2008-04-22
DE2_70_D5M_LTM\Sdram_Control_4Port\control_interface.v 7635 2008-04-22
DE2_70_D5M_LTM\DE2_70.v 18096 2008-08-23
DE2_70_D5M_LTM\V\I2C_CCD_Config.v 8150 2008-06-20
DE2_70_D5M_LTM\V\I2C_Controller.v 4071 2008-05-04
DE2_70_D5M_LTM\V\I2S_Controller.v 3685 2008-04-22
DE2_70_D5M_LTM\V\lcd_3wire_config.v 6185 2008-04-22
DE2_70_D5M_LTM\V\Line_Buffer.v 4825 2008-04-09
DE2_70_D5M_LTM\V\Line_Buffer_dval.v 4776 2008-04-12
DE2_70_D5M_LTM\V\RAW2RGB.v 7886 2008-06-20
DE2_70_D5M_LTM\V\Reset_Delay.v 2325 2008-04-22
DE2_70_D5M_LTM\Sdram_Control_4Port\Sdram_Control_4Port.v 17346 2008-04-22
DE2_70_D5M_LTM\Sdram_Control_4Port\Sdram_FIFO.v 7324 2006-01-05
DE2_70_D5M_LTM\Sdram_Control_4Port\Sdram_PLL.v 17035 2007-08-10
DE2_70_D5M_LTM\V\sdram_pll.v 17186 2008-03-24
DE2_70_D5M_LTM\Sdram_Control_4Port\sdr_data_path.v 2728 2008-04-22
DE2_70_D5M_LTM\V\SEG7_LUT.v 2519 2008-04-22
DE2_70_D5M_LTM\V\SEG7_LUT_8.v 2274 2008-04-22
DE2_70_D5M_LTM\V\touch_tcon.v 5387 2008-08-24
DE2_70_D5M_LTM\V\vga_pll.v 15791 2008-04-09
DE2_70_D5M_LTM\V 0 2008-09-17
DE2_70_D5M_LTM\Sdram_Control_4Port 0 2008-09-17
DE2_70_D5M_LTM\db 0 2008-09-17
DE2_70_D5M_LTM 0 2008-09-17
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