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RISC_CPU

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-02
  • Size : 35kb
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  • Author ：tian****
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Introduction - If you have any usage issues, please Google them yourself
A Verilog based CPU is reloaded on other websites
Packet file list
(Preview for download)
FilenameSizeUpdate
RISC_CPU\accum.v 275 2012-11-26
RISC_CPU\adr.v 162 2012-11-26
RISC_CPU\alu.v 996 2012-11-26
RISC_CPU\alu.v.bak 140 2012-11-26
RISC_CPU\clk_gen.v 1575 2012-11-26
RISC_CPU\counter.v 385 2012-11-26
RISC_CPU\datatcl.v 146 2012-11-26
RISC_CPU\db\RISC_CPU.cmp.rdb 4044 2018-02-02
RISC_CPU\db\RISC_CPU.db_info 140 2018-02-02
RISC_CPU\db\RISC_CPU.map.qmsg 8992 2018-02-02
RISC_CPU\db\RISC_CPU.map.rdb 1196 2018-02-02
RISC_CPU\db\RISC_CPU.map_bb.hdb 9680 2018-02-02
RISC_CPU\db\RISC_CPU.sld_design_entry.sci 223 2018-02-02
RISC_CPU\db\RISC_CPU.smart_action.txt 8 2018-02-02
RISC_CPU\db\RISC_CPU.tis_db_list.ddb 238 2018-02-02
RISC_CPU\machinectl.v 216 2012-11-26
RISC_CPU\register.v 791 2012-11-26
RISC_CPU\RISC_CPU.flow.rpt 6686 2018-02-02
RISC_CPU\RISC_CPU.map.rpt 16953 2018-02-02
RISC_CPU\RISC_CPU.map.summary 673 2018-02-02
RISC_CPU\RISC_CPU.qpf 1270 2012-11-26
RISC_CPU\RISC_CPU.qsf 2878 2018-02-02
RISC_CPU\RISC_CPU.qws 1243 2018-02-02
RISC_CPU\RISC_CPU_assignment_defaults.qdf 55680 2018-02-02
RISC_CPU\db 0 2018-02-02
RISC_CPU 0 2018-02-02
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