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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-03
  • Size : 32kb
  • Downloaded :0次
  • Author :xiaowa******
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
the verilog code project of Tequan Altera cyclone4 FPGA development board
Packet file list
(Preview for download)
FilenameSizeUpdate
cy4ex1\cy4.qpf 1272 2015-08-12
cy4ex1\cy4.qsf 4590 2015-08-31
cy4ex1\cy4.qws 1104 2015-08-31
cy4ex1\cy4_nativelink_simulation.rpt 977 2015-08-31
cy4ex1\output_files\cy4.sof 358638 2015-08-12
cy4ex1\simulation\modelsim\cy4.sft 323 2015-08-12
cy4ex1\simulation\modelsim\cy4.vo 3768 2015-08-12
cy4ex1\simulation\modelsim\cy4.vt 2204 2015-08-12
cy4ex1\simulation\modelsim\cy4_8_1200mv_0c_slow.vo 3785 2015-08-12
cy4ex1\simulation\modelsim\cy4_8_1200mv_0c_v_slow.sdo 2689 2015-08-12
cy4ex1\simulation\modelsim\cy4_8_1200mv_85c_slow.vo 3786 2015-08-12
cy4ex1\simulation\modelsim\cy4_8_1200mv_85c_v_slow.sdo 2702 2015-08-12
cy4ex1\simulation\modelsim\cy4_min_1200mv_0c_fast.vo 3787 2015-08-12
cy4ex1\simulation\modelsim\cy4_min_1200mv_0c_v_fast.sdo 2692 2015-08-12
cy4ex1\simulation\modelsim\cy4_modelsim.xrf 457 2015-08-12
cy4ex1\simulation\modelsim\cy4_run_msim_rtl_verilog.do 625 2015-08-31
cy4ex1\simulation\modelsim\cy4_run_msim_rtl_verilog.do.bak 585 2015-08-12
cy4ex1\simulation\modelsim\cy4_v.sdo 2702 2015-08-12
cy4ex1\simulation\modelsim\modelsim.ini 11131 2015-08-31
cy4ex1\simulation\modelsim\msim_transcript 1849 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4\verilog.prw 201 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4\verilog.psm 2888 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4\_primary.dat 274 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4\_primary.dbs 392 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4\_primary.vhd 211 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4_vlg_tst\verilog.prw 451 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4_vlg_tst\verilog.psm 4808 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4_vlg_tst\_primary.dat 470 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4_vlg_tst\_primary.dbs 655 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4_vlg_tst\_primary.vhd 82 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\_info 1408 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\_vmake 26 2015-08-31
cy4ex1\simulation\modelsim\vsim.wlf 73728 2015-08-31
cy4ex1\source_code\cy4.v 886 2015-08-22
cy4ex1\simulation\modelsim\rtl_work\cy4 0 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\cy4_vlg_tst 0 2015-08-31
cy4ex1\simulation\modelsim\rtl_work\_temp 0 2015-08-31
cy4ex1\simulation\modelsim\rtl_work 0 2015-08-31
cy4ex1\simulation\modelsim 0 2015-08-31
cy4ex1\output_files 0 2015-08-31
cy4ex1\simulation 0 2015-08-25
cy4ex1\source_code 0 2015-08-25
cy4ex1 0 2015-08-31
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