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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-03
  • Size : 922kb
  • Downloaded :0次
  • Author :wybi*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
This module is a common CLK frequency divider; its internal parameters can be dynamically adjusted!
Packet file list
(Preview for download)
FilenameSizeUpdate
clkdiv\.sopc_builder\install.ptf 7303 2008-10-17
clkdiv\clkdiv.asm.rpt 7278 2015-10-30
clkdiv\clkdiv.cdf 326 2008-11-18
clkdiv\clkdiv.done 26 2009-11-21
clkdiv\clkdiv.dpf 239 2009-11-21
clkdiv\clkdiv.eda.rpt 6081 2009-11-21
clkdiv\clkdiv.fit.rpt 48283 2015-10-30
clkdiv\clkdiv.fit.smsg 334 2015-10-30
clkdiv\clkdiv.fit.summary 359 2015-10-30
clkdiv\clkdiv.flow.rpt 10987 2015-10-30
clkdiv\clkdiv.map.rpt 18085 2015-10-30
clkdiv\clkdiv.map.summary 298 2015-10-30
clkdiv\clkdiv.pin 15370 2015-10-30
clkdiv\clkdiv.pof 7854 2015-10-30
clkdiv\clkdiv.qpf 909 2008-10-17
clkdiv\clkdiv.qsf 3588 2015-10-30
clkdiv\clkdiv.qws 577 2015-10-30
clkdiv\clkdiv.sta.rpt 14992 2015-10-30
clkdiv\clkdiv.sta.summary 399 2015-10-30
clkdiv\clkdiv.tan.rpt 14441 2009-11-21
clkdiv\clkdiv.tan.summary 970 2009-11-21
clkdiv\clkdiv.v 728 2018-02-02
clkdiv\clkdiv_assignment_defaults.qdf 40202 2009-03-17
clkdiv\clkdiv_nativelink_simulation.rpt 904 2009-12-29
clkdiv\data.qpd 5193052 2018-01-22
clkdiv\db\clkdiv.db_info 140 2015-10-30
clkdiv\db\clkdiv.ipinfo 163 2015-10-30
clkdiv\db\clkdiv.sld_design_entry.sci 202 2015-10-30
clkdiv\db\clkdiv_global_asgn_op.abo 33561 2009-07-31
clkdiv\db\logic_util_heursitic.dat 176 2015-10-30
clkdiv\db\prev_cmp_clkdiv.asm.qmsg 2188 2015-10-30
clkdiv\db\prev_cmp_clkdiv.eda.qmsg 2736 2015-10-30
clkdiv\db\prev_cmp_clkdiv.fit.qmsg 12079 2015-10-30
clkdiv\db\prev_cmp_clkdiv.map.qmsg 3445 2015-10-30
clkdiv\db\prev_cmp_clkdiv.qmsg 24807 2015-10-30
clkdiv\db\prev_cmp_clkdiv.sta.qmsg 6923 2015-10-30
clkdiv\db\prev_cmp_clkdiv.tan.qmsg 17251 2015-10-30
clkdiv\incremental_db\compiled_partitions\clkdiv.db_info 140 2015-10-30
clkdiv\incremental_db\compiled_partitions\clkdiv.root_partition.map.kpt 300 2015-10-30
clkdiv\incremental_db\README 653 2009-03-17
clkdiv\simulation\modelsim\clkdiv.sft 114 2009-11-21
clkdiv\simulation\modelsim\clkdiv.vo 3444 2009-11-21
clkdiv\simulation\modelsim\clkdiv.vt 2221 2009-11-20
clkdiv\simulation\modelsim\clkdiv_modelsim.xrf 317 2009-11-21
clkdiv\simulation\modelsim\clkdiv_run_msim_gate_verilog.do 511 2009-12-29
clkdiv\simulation\modelsim\clkdiv_run_msim_gate_verilog.do.bak1 514 2009-11-21
clkdiv\simulation\modelsim\clkdiv_run_msim_gate_verilog.do.bak2 511 2009-12-29
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do 587 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak1 586 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak2 586 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak3 586 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak4 587 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak5 587 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak6 587 2009-11-20
clkdiv\simulation\modelsim\clkdiv_run_msim_rtl_verilog.do.bak7 587 2009-11-20
clkdiv\simulation\modelsim\clkdiv_v.sdo 2593 2009-11-21
clkdiv\simulation\modelsim\clkdiv_v.sdo_typ.csd 578 2009-11-21
clkdiv\simulation\modelsim\gate_work\clkdiv\verilog.prw 4152 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv\verilog.psm 11144 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv\_primary.dat 1662 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv\_primary.dbs 3905 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv\_primary.vhd 217 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv_vlg_tst\verilog.prw 1464 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv_vlg_tst\verilog.psm 4608 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv_vlg_tst\_primary.dat 391 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv_vlg_tst\_primary.dbs 887 2009-12-29
clkdiv\simulation\modelsim\gate_work\clkdiv_vlg_tst\_primary.vhd 88 2009-12-29
clkdiv\simulation\modelsim\gate_work\_info 694 2009-12-29
clkdiv\simulation\modelsim\gate_work\_vmake 26 2009-12-29
clkdiv\simulation\modelsim\modelsim.ini 11084 2009-12-29
clkdiv\simulation\modelsim\msim_transcript 2146 2009-12-29
clkdiv\simulation\modelsim\rtl_work\clkdiv\verilog.prw 1088 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv\verilog.psm 3440 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv\_primary.dat 303 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv\_primary.dbs 716 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv\_primary.vhd 217 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv_vlg_tst\verilog.prw 1464 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv_vlg_tst\verilog.psm 4608 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv_vlg_tst\_primary.dat 391 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv_vlg_tst\_primary.dbs 888 2009-11-20
clkdiv\simulation\modelsim\rtl_work\clkdiv_vlg_tst\_primary.vhd 88 2009-11-20
clkdiv\simulation\modelsim\rtl_work\_info 803 2009-11-20
clkdiv\simulation\modelsim\rtl_work\_vmake 26 2009-11-20
clkdiv\simulation\modelsim\vsim.wlf 40960 2009-12-29
clkdiv\sopc_builder_debug_log.txt 0 2008-10-17
clkdiv\undo_redo.txt 72 2009-11-21
clkdiv\simulation\modelsim\gate_work\clkdiv 0 2018-02-03
clkdiv\simulation\modelsim\gate_work\clkdiv_vlg_tst 0 2018-02-03
clkdiv\simulation\modelsim\gate_work\_temp 0 2015-10-17
clkdiv\simulation\modelsim\rtl_work\clkdiv 0 2018-02-03
clkdiv\simulation\modelsim\rtl_work\clkdiv_vlg_tst 0 2018-02-03
clkdiv\simulation\modelsim\rtl_work\_temp 0 2015-10-17
clkdiv\simulation\modelsim\gate_work 0 2018-02-03
clkdiv\simulation\modelsim\rtl_work 0 2018-02-03
clkdiv\incremental_db\compiled_partitions 0 2018-02-03
clkdiv\simulation\modelsim 0 2018-02-03
clkdiv\.sopc_builder 0 2018-02-03
clkdiv\db 0 2018-02-03
clkdiv\incremental_db 0 2018-02-03
clkdiv\simulation 0 2018-02-03
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