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just_clock

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-22
  • Size : 538kb
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  • Author ：Ivr***
  • About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Just a clock made for basys3 in vivado.
Packet file list
(Preview for download)
FilenameSizeUpdate
clk\clk.cache 0 2018-02-02
clk\clk.cache\compile_simlib 0 2018-02-02
clk\clk.cache\compile_simlib\activehdl 0 2018-02-02
clk\clk.cache\compile_simlib\ies 0 2018-02-02
clk\clk.cache\compile_simlib\modelsim 0 2018-02-02
clk\clk.cache\compile_simlib\questa 0 2018-02-02
clk\clk.cache\compile_simlib\riviera 0 2018-02-02
clk\clk.cache\compile_simlib\vcs 0 2018-02-02
clk\clk.cache\ip 0 2018-02-02
clk\clk.cache\ip\2017.4 0 2018-02-02
clk\clk.cache\wt 0 2018-02-02
clk\clk.cache\wt\gui_handlers.wdf 788 2018-02-02
clk\clk.cache\wt\gui_resources.wdf 3715 2018-02-02
clk\clk.cache\wt\java_command_handlers.wdf 1501 2018-02-02
clk\clk.cache\wt\project.wpc 121 2018-02-02
clk\clk.cache\wt\synthesis.wdf 5408 2018-02-02
clk\clk.cache\wt\synthesis_details.wdf 100 2018-02-02
clk\clk.cache\wt\webtalk_pa.xml 2625 2018-02-02
clk\clk.cache\wt\xsim.wdf 256 2018-02-02
clk\clk.hw 0 2018-02-02
clk\clk.hw\clk.lpr 343 2018-02-02
clk\clk.hw\hw_1 0 2018-02-02
clk\clk.hw\hw_1\hw.xml 743 2018-02-02
clk\clk.hw\hw_1\wave 0 2018-02-02
clk\clk.ip_user_files 0 2018-02-02
clk\clk.ip_user_files\README.txt 130 2018-02-02
clk\clk.runs 0 2018-02-02
clk\clk.runs\.jobs 0 2018-02-02
clk\clk.runs\.jobs\vrs_config_1.xml 208 2018-02-02
clk\clk.runs\.jobs\vrs_config_2.xml 222 2018-02-02
clk\clk.runs\.jobs\vrs_config_3.xml 229 2018-02-02
clk\clk.runs\impl_1 0 2018-02-02
clk\clk.runs\impl_1\_init_design.begin.rst 181 2018-02-02
clk\clk.runs\impl_1\_init_design.end.rst 0 2018-02-02
clk\clk.runs\impl_1\_opt_design.begin.rst 181 2018-02-02
clk\clk.runs\impl_1\_opt_design.end.rst 0 2018-02-02
clk\clk.runs\impl_1\_place_design.begin.rst 181 2018-02-02
clk\clk.runs\impl_1\_place_design.end.rst 0 2018-02-02
clk\clk.runs\impl_1\_route_design.begin.rst 181 2018-02-02
clk\clk.runs\impl_1\_route_design.end.rst 0 2018-02-02
clk\clk.runs\impl_1\_vivado.begin.rst 361 2018-02-02
clk\clk.runs\impl_1\_vivado.end.rst 0 2018-02-02
clk\clk.runs\impl_1\_Vivado_Implementation.queue.rst 0 2018-02-02
clk\clk.runs\impl_1\_write_bitstream.begin.rst 182 2018-02-02
clk\clk.runs\impl_1\_write_bitstream.end.rst 0 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz.bit 2192125 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz.tcl 1797 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz.vdi 24529 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_8940.backup.vdi 19756 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_clock_utilization_routed.rpt 10699 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_control_sets_placed.rpt 2922 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_drc_opted.rpt 2251 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_drc_routed.pb 37 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_drc_routed.rpt 2435 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_drc_routed.rpx 1639 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_io_placed.rpt 61749 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_methodology_drc_routed.rpt 1628 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_methodology_drc_routed.rpx 390 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_opt.dcp 124962 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_placed.dcp 131397 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_power_routed.rpt 7436 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_power_routed.rpx 13654 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_power_summary_routed.pb 711 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_route_status.pb 43 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_route_status.rpt 588 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_routed.dcp 136836 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_timing_summary_routed.rpt 101167 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_timing_summary_routed.rpx 77056 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_utilization_placed.pb 276 2018-02-02
clk\clk.runs\impl_1\Div_100Mhz_to_1Hz_utilization_placed.rpt 8775 2018-02-02
clk\clk.runs\impl_1\gen_run.xml 3357 2018-02-02
clk\clk.runs\impl_1\htr.txt 419 2018-02-02
clk\clk.runs\impl_1\init_design.pb 1608 2018-02-02
clk\clk.runs\impl_1\ISEWrap.js 7308 2018-02-02
clk\clk.runs\impl_1\ISEWrap.sh 1623 2018-02-02
clk\clk.runs\impl_1\opt_design.pb 7124 2018-02-02
clk\clk.runs\impl_1\place_design.pb 13366 2018-02-02
clk\clk.runs\impl_1\project.wdf 3626 2018-02-02
clk\clk.runs\impl_1\route_design.pb 12527 2018-02-02
clk\clk.runs\impl_1\rundef.js 1416 2018-02-02
clk\clk.runs\impl_1\runme.bat 229 2018-02-02
clk\clk.runs\impl_1\runme.log 24387 2018-02-02
clk\clk.runs\impl_1\runme.sh 1270 2018-02-02
clk\clk.runs\impl_1\usage_statistics_webtalk.html 20835 2018-02-02
clk\clk.runs\impl_1\usage_statistics_webtalk.xml 28310 2018-02-02
clk\clk.runs\impl_1\vivado.jou 723 2018-02-02
clk\clk.runs\impl_1\vivado.pb 149 2018-02-02
clk\clk.runs\impl_1\vivado_8940.backup.jou 722 2018-02-02
clk\clk.runs\impl_1\write_bitstream.pb 6762 2018-02-02
clk\clk.runs\synth_1 0 2018-02-02
clk\clk.runs\synth_1\.Xil 0 2018-02-02
clk\clk.runs\synth_1\.Xil\Div_100Mhz_to_1Hz_propImpl.xdc 494 2018-02-02
clk\clk.runs\synth_1\_vivado.begin.rst 180 2018-02-02
clk\clk.runs\synth_1\_vivado.end.rst 0 2018-02-02
clk\clk.runs\synth_1\_Vivado_Synthesis.queue.rst 0 2018-02-02
clk\clk.runs\synth_1\Div_100Mhz_to_1Hz.dcp 14653 2018-02-02
clk\clk.runs\synth_1\Div_100Mhz_to_1Hz.tcl 1863 2018-02-02
clk\clk.runs\synth_1\Div_100Mhz_to_1Hz.vds 16791 2018-02-02
clk\clk.runs\synth_1\Div_100Mhz_to_1Hz_utilization_synth.pb 276 2018-02-02
clk\clk.runs\synth_1\Div_100Mhz_to_1Hz_utilization_synth.rpt 7113 2018-02-02
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