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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-24
  • Size : 1.68mb
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  • Author :jet****
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Introduction - If you have any usage issues, please Google them yourself
The 32 bit ALU is realized by using the Booth algorithm.
Packet file list
(Preview for download)
FilenameSizeUpdate
ALU32\32位ALU设计报告.docx 639268 2017-05-14
ALU32\32位ALU设计报告.pdf 1418919 2017-05-14
ALU32\ADD_32.v 1599 2017-05-13
ALU32\ADD_4.v 2044 2017-05-13
ALU32\ALU.v 5238 2017-05-13
ALU32\ALU_tb.v 2364 2017-05-13
ALU32\DIV_32.v 1420 2017-05-13
ALU32\MUL_32.v 2506 2017-05-13
ALU32\RTL_View.pdf 724536 2017-05-14
ALU32 0 2018-02-24
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