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bcd counter

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-25
  • Size : 172kb
  • Downloaded :0次
  • Author :Arma****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Binary counter design in verilog
Packet file list
(Preview for download)
FilenameSizeUpdate
bcd counter 0 2016-12-18
bcd counter\bcd counter.cr.mti 1347 2016-12-15
bcd counter\bcd counter.mpf 14504 2016-12-15
bcd counter\bcd_7seg.v 800 2016-12-15
bcd counter\bcd_count.v 319 2016-12-15
bcd counter\clk_div.v 462 2016-12-15
bcd counter\tb_test.v 836 2016-12-15
bcd counter\top_counter.v 440 2016-05-13
bcd counter\vsim.wlf 770048 2016-05-13
bcd counter\vsim_stacktrace.vstf 683 2016-05-13
bcd counter\work 0 2016-12-18
bcd counter\work\bcd7segdec 0 2016-12-18
bcd counter\work\bcd7segdec\verilog.asm 4008 2016-12-15
bcd counter\work\bcd7segdec\_primary.dat 842 2016-12-15
bcd counter\work\bcd7segdec\_primary.vhd 282 2016-12-15
bcd counter\work\bcd_count 0 2016-12-18
bcd counter\work\bcd_count\verilog.asm 3312 2016-12-15
bcd counter\work\bcd_count\_primary.dat 378 2016-12-15
bcd counter\work\bcd_count\_primary.vhd 242 2016-12-15
bcd counter\work\clk_div_1hz 0 2016-12-18
bcd counter\work\clk_div_1hz\verilog.asm 3923 2016-12-15
bcd counter\work\clk_div_1hz\_primary.dat 437 2016-12-15
bcd counter\work\clk_div_1hz\_primary.vhd 227 2016-12-15
bcd counter\work\tb_test 0 2016-12-18
bcd counter\work\tb_test\verilog.asm 3725 2016-12-15
bcd counter\work\tb_test\_primary.dat 385 2016-12-15
bcd counter\work\tb_test\_primary.vhd 74 2016-12-15
bcd counter\work\top_count 0 2016-12-18
bcd counter\work\top_count\verilog.asm 3569 2016-12-15
bcd counter\work\top_count\_primary.dat 519 2016-12-15
bcd counter\work\top_count\_primary.vhd 304 2016-12-15
bcd counter\work\_info 1039 2016-12-15
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