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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-02-26
  • Size : 40kb
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  • Author ：蝶*****
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Introduction - If you have any usage issues, please Google them yourself
Implementation of UDP/IP protocol with FPGA
Packet file list
(Preview for download)
FilenameSizeUpdate
imports\imports\ac701_ethernet_rgmii_fifo_block.v 11600 2017-10-10
imports\imports\ac701_ethernet_rgmii_reset_sync.v 4562 2017-07-24
imports\imports\ac701_ethernet_rgmii_support.v 11503 2017-10-10
imports\imports\ac701_ethernet_rgmii_support_clocking.v 6532 2017-07-24
imports\imports\ac701_ethernet_rgmii_support_resets.v 6891 2017-07-24
imports\new\ac701_ethernet_comm.v 12093 2017-11-18
imports\new\data_out_transfer.v 4515 2017-08-18
imports\new\ethernet_trans_cache.v 2861 2017-10-25
imports\new\freq_band_num_transfer.v 4283 2017-08-23
imports\sources_1\imports\imports\ac701_ethernet_rgmii_axi_lite_sm.v 28589 2017-10-10
imports\sources_1\imports\imports\ac701_ethernet_rgmii_sync_block.v 4670 2017-10-09
imports\sources_1\new\Ethenet_Frame_Generator.v 24727 2017-11-19
imports\sources_1\new\Ethernet_Frame_Receiver.v 31237 2017-11-18
imports\sources_1\new\TR_time_transfer.v 21446 2017-08-23
imports\sources_1\imports\imports 0 2017-10-23
imports\sources_1\imports 0 2017-10-23
imports\sources_1\new 0 2017-10-23
imports\imports 0 2017-10-23
imports\new 0 2017-12-28
imports\sources_1 0 2017-10-23
imports 0 2017-10-23
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