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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-03-02
  • Size : 6.02mb
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  • Author :i be****
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Introduction - If you have any usage issues, please Google them yourself
The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates a clock signal after a second second, also provides the clock display function module display module to scan the counter.
Packet file list
(Preview for download)
FilenameSizeUpdate
dif\db\dif.(0).cnf.cdb 3327 2017-05-06
dif\db\dif.(0).cnf.hdb 1500 2017-05-06
dif\db\dif.ace_cmp.bpm 539 2017-05-06
dif\db\dif.ace_cmp.cdb 13225 2017-05-06
dif\db\dif.ace_cmp.hdb 11483 2017-05-06
dif\db\dif.amm.cdb 296 2017-05-06
dif\db\dif.asm.qmsg 2208 2017-05-06
dif\db\dif.asm.rdb 1313 2017-05-06
dif\db\dif.asm_labs.ddb 7338 2017-05-06
dif\db\dif.cbx.xml 85 2017-05-06
dif\db\dif.cmp.bpm 539 2017-05-06
dif\db\dif.cmp.cdb 13225 2017-05-06
dif\db\dif.cmp.hdb 11483 2017-05-06
dif\db\dif.cmp.kpt 199 2017-05-06
dif\db\dif.cmp.logdb 8243 2017-05-06
dif\db\dif.cmp.rdb 17934 2017-05-06
dif\db\dif.cmp_merge.kpt 205 2017-05-06
dif\db\dif.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 746335 2017-05-06
dif\db\dif.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 745242 2017-05-06
dif\db\dif.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 740231 2017-05-06
dif\db\dif.db_info 138 2017-04-16
dif\db\dif.eco.cdb 160 2017-05-06
dif\db\dif.eda.qmsg 4776 2017-05-06
dif\db\dif.fit.qmsg 21835 2017-05-06
dif\db\dif.hier_info 983 2017-05-06
dif\db\dif.hif 643 2017-05-06
dif\db\dif.idb.cdb 2524 2017-05-06
dif\db\dif.lpc.html 430 2017-05-06
dif\db\dif.lpc.rdb 388 2017-05-06
dif\db\dif.lpc.txt 1060 2017-05-06
dif\db\dif.map.bpm 514 2017-05-06
dif\db\dif.map.cdb 4728 2017-05-06
dif\db\dif.map.hdb 10801 2017-05-06
dif\db\dif.map.kpt 1109 2017-05-06
dif\db\dif.map.logdb 4 2017-05-06
dif\db\dif.map.qmsg 5444 2017-05-06
dif\db\dif.map_bb.cdb 1002 2017-05-06
dif\db\dif.map_bb.hdb 8643 2017-05-06
dif\db\dif.map_bb.logdb 4 2017-05-06
dif\db\dif.pre_map.cdb 3092 2017-05-06
dif\db\dif.pre_map.hdb 10000 2017-05-06
dif\db\dif.rpp.qmsg 1833 2017-04-16
dif\db\dif.rtlv.hdb 9997 2017-05-06
dif\db\dif.rtlv_sg.cdb 2668 2017-05-06
dif\db\dif.rtlv_sg_swap.cdb 177 2017-05-06
dif\db\dif.sgate.rvd 2171 2017-04-16
dif\db\dif.sgate_sm.rvd 212 2017-04-16
dif\db\dif.sgdiff.cdb 4363 2017-05-06
dif\db\dif.sgdiff.hdb 10520 2017-05-06
dif\db\dif.sld_design_entry.sci 214 2018-03-02
dif\db\dif.sld_design_entry_dsc.sci 196 2017-05-06
dif\db\dif.smart_action.txt 8 2017-05-06
dif\db\dif.sta.qmsg 19947 2017-05-06
dif\db\dif.sta.rdb 15560 2017-05-06
dif\db\dif.sta_cmp.8_slow_1200mv_85c.tdb 15886 2017-05-06
dif\db\dif.syn_hier_info 0 2017-05-06
dif\db\dif.tiscmp.fastest_slow_1200mv_0c.ddb 114085 2017-05-06
dif\db\dif.tiscmp.fastest_slow_1200mv_85c.ddb 114209 2017-05-06
dif\db\dif.tiscmp.fast_1200mv_0c.ddb 146039 2017-05-06
dif\db\dif.tiscmp.slow_1200mv_0c.ddb 147399 2017-05-06
dif\db\dif.tiscmp.slow_1200mv_85c.ddb 147001 2017-05-06
dif\db\dif.tis_db_list.ddb 231 2017-05-06
dif\db\dif.tmw_info 310 2018-03-02
dif\db\logic_util_heursitic.dat 5192 2017-05-06
dif\db\prev_cmp_dif.qmsg 54712 2017-05-06
dif\dif.asm.rpt 6471 2017-05-06
dif\dif.bsf 1749 2017-04-16
dif\dif.done 26 2017-05-06
dif\dif.eda.rpt 6915 2017-05-06
dif\dif.fit.rpt 136865 2017-05-06
dif\dif.fit.smsg 513 2017-05-06
dif\dif.fit.summary 593 2017-05-06
dif\dif.flow.rpt 8954 2017-05-06
dif\dif.map.rpt 20387 2017-05-06
dif\dif.map.summary 457 2017-05-06
dif\dif.pin 33075 2017-05-06
dif\dif.qpf 1268 2017-04-16
dif\dif.qsf 3591 2018-03-02
dif\dif.sof 358324 2017-05-06
dif\dif.sta.rpt 157521 2017-05-06
dif\dif.sta.summary 951 2017-05-06
dif\dif.tis_db_list.ddb 231 2017-05-06
dif\dif_nativelink_simulation.rpt 827 2017-05-06
dif\incremental_db\compiled_partitions\dif.db_info 138 2017-04-16
dif\incremental_db\compiled_partitions\dif.root_partition.cmp.cdb 5932 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.cmp.dfp 33 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.cmp.hdb 11084 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.cmp.kpt 204 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.cmp.logdb 4 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.cmp.rcfdb 6059 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.cdb 4547 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.dpi 615 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.hbdb.cdb 608 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.hbdb.hb_info 46 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.hbdb.hdb 10455 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.hbdb.sig 31 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.hdb 10805 2017-05-06
dif\incremental_db\compiled_partitions\dif.root_partition.map.kpt 1118 2017-05-06
dif\incremental_db\README 653 2017-04-16
dif\simulation\modelsim\dif.sft 322 2017-05-06
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