| Filename | Size | Update |
|---|
| -FPGA-PLD--master | 0 | 2017-05-20
|
| -FPGA-PLD--master\LICENSE | 7651 | 2017-05-20
|
| -FPGA-PLD--master\README.md | 150 | 2017-05-20
|
| -FPGA-PLD--master\elec_design | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1 | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\sim | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\sim\tb_state.v | 1536 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\src | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\src\key.v | 3026 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\src\motor.v | 2507 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\src\pwm.v | 3402 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\src\state.v | 4169 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta1\src\top.v | 2600 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2 | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\sim | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\sim\tb_pwm.v | 906 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\sim\tb_state.v | 1536 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\src | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\src\key.v | 3026 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\src\motor.v | 2507 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\src\pwm.v | 3862 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\src\state.v | 5672 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta2\src\top.v | 2600 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3 | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\sim | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\sim\tb_pwm.v | 906 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\sim\tb_state.v | 1536 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\src | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\src\key.v | 3026 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\src\motor.v | 2507 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\src\pwm.v | 4197 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\src\state.v | 6335 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta3\src\top.v | 3051 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4 | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\sim | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\sim\tb_pwm.v | 906 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\sim\tb_state.v | 1536 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\src | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\src\key.v | 3026 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\src\motor.v | 2507 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\src\pwm.v | 4221 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\src\state.v | 6343 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\beta4\src\top.v | 3057 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\sim | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\sim\tb_state.v | 1536 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\src | 0 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\src\key.v | 3026 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\src\motor.v | 2507 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\src\pwm.v | 3402 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\src\state.v | 5620 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\release\src\top.v | 2786 | 2017-05-20
|
| -FPGA-PLD--master\elec_design\控制组.pdf | 407993 | 2017-05-20 |