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RedPitayaPID-master

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-03-08
  • Size : 6.07mb
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  • Author ：余***
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Introduction - If you have any usage issues, please Google them yourself
Multi-Channel PID Controller Implemented on the Red Pitaya Created as part of a summer research project for the Ultracold Quantum Matter group, Department of Atomic & Laser Physics, University of Oxford.
Packet file list
(Preview for download)
FilenameSizeUpdate
RedPitayaPID-master 0 2017-12-19
RedPitayaPID-master\FPGA 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\constrs_1 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\constrs_1\designprops.xml 121 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\constrs_1\fileset.xml 1481 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\constrs_1\usercols.xml 73 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\impl_1.psg 728 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\impl_1 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\impl_1\constrs_in.xml 1160 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\impl_1\impl_1.psg 728 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\runs.xml 3805 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\synth_1.psg 377 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\synth_1 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\synth_1\constrs_in.xml 1160 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\synth_1\sources.xml 7890 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\runs\synth_1\synth_1.psg 377 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\sim_1 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\sim_1\fileset.xml 373 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\sources_1 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\sources_1\fileset.xml 8053 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\sources_1\ports.xml 7631 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\wt 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\wt\java_command_handlers.wdf 287 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\wt\project.wpc 58 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\wt\synthesis.wdf 3183 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\wt\webtalk_pa.xml 1263 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.data\wt\xsim.wdf 235 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs 0 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_1.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_10.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_100.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_101.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_102.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_103.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_104.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_105.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_106.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_107.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_108.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_109.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_11.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_110.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_111.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_112.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_113.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_114.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_115.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_116.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_117.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_118.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_119.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_12.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_120.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_121.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_122.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_123.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_124.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_125.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_126.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_127.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_128.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_129.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_13.xml 226 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_130.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_131.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_132.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_133.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_134.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_135.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_136.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_137.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_138.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_139.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_14.xml 240 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_140.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_141.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_142.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_143.xml 254 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_144.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_145.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_146.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_147.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_148.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_149.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_15.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_150.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_151.xml 254 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_152.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_153.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_154.xml 254 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_155.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_156.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_157.xml 254 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_158.xml 233 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_159.xml 247 2017-12-19
RedPitayaPID-master\FPGA\Vivado\red_pitaya.runs\.jobs\vrs_config_16.xml 226 2017-12-19
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