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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2018-03-17
- Size : 2kb
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- Author ：大*****
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.
Packet file list
(Preview for download)
| Filename | Size | Update |
|---|---|---|
| FIFO_RD.v | 350 | 2017-11-01 |
| FIFO_STATUS.v | 648 | 2017-11-01 |
| FIFO_WR.v | 342 | 2017-11-01 |
| RD_ptr_empty.v | 884 | 2017-11-25 |
| Sync_RD.v | 367 | 2017-11-25 |
| Sync_WR.v | 365 | 2017-11-25 |
| WR_ptr_full.v | 920 | 2017-11-25 |
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