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uart_txd

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-03-17
  • Size : 192kb
  • Downloaded :0次
  • Author :xd***
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Introduction - If you have any usage issues, please Google them yourself
Serial data transmission module implemented with VHDL.The software used is ISE and modelsim.
Packet file list
(Preview for download)
FilenameSizeUpdate
uart_txd 0 2017-11-03
uart_txd\_xmsgs 0 2017-11-03
uart_txd\_xmsgs\pn_parser.xmsgs 766 2017-11-03
uart_txd\_xmsgs\xst.xmsgs 367 2017-11-03
uart_txd\ipcore_dir 0 2018-03-17
uart_txd\iseconfig 0 2017-11-03
uart_txd\iseconfig\uart_txd.projectmgr 7713 2017-11-03
uart_txd\iseconfig\uart_txd.xreport 20583 2017-11-03
uart_txd\modelsim.ini 11618 2017-11-03
uart_txd\pepExtractor.prj 21 2017-11-03
uart_txd\transcript 2477 2017-11-03
uart_txd\uart_txd.cmd_log 280 2017-11-03
uart_txd\uart_txd.fdo 1169 2017-11-03
uart_txd\uart_txd.gise 7988 2017-11-03
uart_txd\uart_txd.lso 6 2017-11-03
uart_txd\uart_txd.ngc 5046 2017-11-03
uart_txd\uart_txd.ngr 6713 2017-11-03
uart_txd\uart_txd.prj 26 2017-11-03
uart_txd\uart_txd.stx 0 2017-11-03
uart_txd\uart_txd.syr 14902 2017-11-03
uart_txd\uart_txd.udo 381 2017-11-03
uart_txd\uart_txd.vhd 1725 2017-11-03
uart_txd\uart_txd.xise 40450 2017-11-03
uart_txd\uart_txd.xst 1073 2017-11-03
uart_txd\uart_txd_envsettings.html 9342 2017-11-03
uart_txd\uart_txd_summary.html 5061 2017-11-03
uart_txd\uart_txd_tb.fdo 1220 2017-11-03
uart_txd\uart_txd_tb.udo 384 2017-11-03
uart_txd\uart_txd_tb.vhd 1529 2017-11-03
uart_txd\uart_txd_tb_wave.fdo 409 2017-11-03
uart_txd\uart_txd_wave.fdo 406 2017-11-03
uart_txd\uart_txd_xst.xrpt 12900 2017-11-03
uart_txd\vsim.wlf 49152 2017-11-03
uart_txd\webtalk_pn.xml 3027 2017-11-03
uart_txd\work 0 2017-11-03
uart_txd\work\@_opt 0 2017-11-03
uart_txd\work\@_opt\_lib.qdb 49152 2017-11-03
uart_txd\work\@_opt\_lib1_0.qdb 32768 2017-11-03
uart_txd\work\@_opt\_lib1_0.qpg 16384 2017-11-03
uart_txd\work\@_opt\_lib1_0.qtl 5862 2017-11-03
uart_txd\work\@_opt\_lib2_0.qdb 32768 2017-11-03
uart_txd\work\@_opt\_lib2_0.qpg 24576 2017-11-03
uart_txd\work\@_opt\_lib2_0.qtl 22038 2017-11-03
uart_txd\work\@_opt\_lib3_0.qdb 32768 2017-11-03
uart_txd\work\@_opt\_lib3_0.qpg 0 2017-11-03
uart_txd\work\@_opt\_lib3_0.qtl 2139 2017-11-03
uart_txd\work\@_opt\_lib4_0.qdb 32768 2017-11-03
uart_txd\work\@_opt\_lib4_0.qpg 16384 2017-11-03
uart_txd\work\@_opt\_lib4_0.qtl 6782 2017-11-03
uart_txd\work\@_opt1 0 2017-11-03
uart_txd\work\@_opt1\_lib.qdb 49152 2017-11-03
uart_txd\work\@_opt1\_lib1_0.qdb 32768 2017-11-03
uart_txd\work\@_opt1\_lib1_0.qpg 16384 2017-11-03
uart_txd\work\@_opt1\_lib1_0.qtl 22912 2017-11-03
uart_txd\work\@_opt1\_lib2_0.qdb 32768 2017-11-03
uart_txd\work\@_opt1\_lib2_0.qpg 24576 2017-11-03
uart_txd\work\@_opt1\_lib2_0.qtl 27282 2017-11-03
uart_txd\work\@_opt1\_lib3_0.qdb 32768 2017-11-03
uart_txd\work\@_opt1\_lib3_0.qpg 0 2017-11-03
uart_txd\work\@_opt1\_lib3_0.qtl 9603 2017-11-03
uart_txd\work\@_opt1\_lib4_0.qdb 32768 2017-11-03
uart_txd\work\@_opt1\_lib4_0.qpg 32768 2017-11-03
uart_txd\work\@_opt1\_lib4_0.qtl 9340 2017-11-03
uart_txd\work\@_opt1\_lib5_0.qdb 32768 2017-11-03
uart_txd\work\@_opt1\_lib5_0.qpg 16384 2017-11-03
uart_txd\work\@_opt1\_lib5_0.qtl 2156 2017-11-03
uart_txd\work\@_opt1\_lib6_0.qdb 32768 2017-11-03
uart_txd\work\@_opt1\_lib6_0.qpg 16384 2017-11-03
uart_txd\work\@_opt1\_lib6_0.qtl 2156 2017-11-03
uart_txd\work\_info 1648 2017-11-03
uart_txd\work\_lib.qdb 49152 2017-11-03
uart_txd\work\_lib1_0.qdb 32768 2017-11-03
uart_txd\work\_lib1_0.qpg 16384 2017-11-03
uart_txd\work\_lib1_0.qtl 37844 2017-11-03
uart_txd\work\_temp 0 2018-03-17
uart_txd\work\_tempmsg 0 2018-03-17
uart_txd\work\_vmake 29 2017-11-03
uart_txd\xst 0 2017-11-03
uart_txd\xst\dump.xst 0 2017-11-03
uart_txd\xst\dump.xst\uart_txd.prj 0 2018-03-17
uart_txd\xst\projnav.tmp 0 2018-03-17
uart_txd\xst\work 0 2017-11-03
uart_txd\xst\work\work.vdbl 5534 2017-11-03
uart_txd\xst\work\work.vdbx 70 2017-11-03
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