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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-03-21
  • Size : 114kb
  • Downloaded :0次
  • Author :Imma****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Code to synthesize Arithmetic Logic Unit
Packet file list
(Preview for download)
FilenameSizeUpdate
alu.asm.rpt 7453 2018-03-07
alu.done 26 2018-03-07
alu.dpf 239 2018-03-07
alu.fit.rpt 206998 2018-03-07
alu.fit.smsg 513 2018-03-07
alu.fit.summary 593 2018-03-07
alu.flow.rpt 7676 2018-03-07
alu.map.rpt 20369 2018-03-07
alu.map.summary 446 2018-03-07
alu.pin 103877 2018-03-07
alu.pof 2097339 2018-03-07
alu.qpf 1259 2018-03-06
alu.qsf 4115 2018-03-07
alu.qws 90 2018-03-07
alu.sim.rpt 11092 2018-03-07
alu.sof 1768869 2018-03-07
alu.tan.rpt 11726 2018-03-07
alu.tan.summary 726 2018-03-07
alu.vhd 1075 2018-03-07
alu.vhd.bak 1080 2018-03-06
alu.vwf 6465 2018-03-07
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