| Filename | Size | Update |
|---|
| project_scCPU\project_scCPU.cache\wt\gui_resources.wdf | 4475 | 2017-11-27
|
| project_scCPU\project_scCPU.cache\wt\java_command_handlers.wdf | 991 | 2017-11-27
|
| project_scCPU\project_scCPU.cache\wt\project.wpc | 61 | 2017-11-27
|
| project_scCPU\project_scCPU.cache\wt\webtalk_pa.xml | 4587 | 2017-11-27
|
| project_scCPU\project_scCPU.cache\wt\xsim.wdf | 256 | 2017-11-27
|
| project_scCPU\project_scCPU.hw\project_scCPU.lpr | 290 | 2017-11-27
|
| project_scCPU\project_scCPU.ip_user_files\README.txt | 130 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\compile.bat | 319 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\compile.log | 4048 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\glbl.v | 1470 | 2017-01-24
|
| project_scCPU\project_scCPU.sim\sim_1\behav\scCPU_sim_vlog.prj | 1353 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\xsim.dir\xsim.svtype | 8 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\xsim.ini | 40 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\xvlog.log | 4048 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\xvlog.pb | 6909 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sim_1\new\scCPU_sim.v | 1000 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\ALU.v | 1697 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\contrUnit.v | 2898 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\dataMemory.v | 1447 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\instrMemory.v | 1129 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\mux_2to1_32bit.v | 795 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\mux_2to1_5bit.v | 827 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\PC.v | 977 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\regFile.v | 1305 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\signZeroExtend.v | 1120 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\singleCycleCPU.v | 2978 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\unit1.v | 1693 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\unit2.v | 1602 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\unit3.v | 1197 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new\unit4.v | 1475 | 2017-11-27
|
| project_scCPU\project_scCPU.xpr | 9808 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\xsim.dir\xil_defaultlib | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav\xsim.dir | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1\behav | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sim_1\new | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1\new | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.cache\wt | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.sim\sim_1 | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sim_1 | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs\sources_1 | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.cache | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.hw | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.ip_user_files | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.sim | 0 | 2017-11-27
|
| project_scCPU\project_scCPU.srcs | 0 | 2017-11-27
|
| project_scCPU | 0 | 2017-11-27 |