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NetFPGA-1G-CML

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-03-31
  • Size : 87.11mb
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  • Author ：蓦*****
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Introduction - If you have any usage issues, please Google them yourself
The basic functions of netFPGA card are as follows: NIC, router, etc.
Packet file list
(Preview for download)
FilenameSizeUpdate
NetFPGA-1G-CML\.gitignore 497 2016-10-21
NetFPGA-1G-CML\bashrc_addon_NetFPGA_10G 313 2017-06-12
NetFPGA-1G-CML\docs\HTG-V5TXT-PCIE_Schematic.pdf 1373226 2016-10-21
NetFPGA-1G-CML\docs\HTG-V5TXT-PCIE_UserManual.pdf 1494092 2016-10-21
NetFPGA-1G-CML\docs\top_UCF.ucf 56516 2016-10-21
NetFPGA-1G-CML\LGPL-2.1 26530 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\mdio_ctrl_v1_00_a\data\mdio_ctrl_v2_1_0.mpd 4229 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\mdio_ctrl_v1_00_a\data\mdio_ctrl_v2_1_0.pao 1437 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\mdio_ctrl_v1_00_a\hdl\vhdl\mdio_ctrl.vhd 10267 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\mdio_ctrl_v1_00_a\hdl\vhdl\mdio_ctrl_core.vhd 5580 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\mdio_ctrl_v1_00_a\Makefile 1284 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\mdio_ctrl_v1_00_a\README 2492 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\data\nf10_arp_reply_v2_1_0.mpd 4791 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\data\nf10_arp_reply_v2_1_0.pao 1458 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\fallthrough_small_fifo_v2.v 3291 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\mac_addr_lookup.v 9249 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\nf10_arp_reply.v 9519 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\nf10_arp_reply_tb.prj 181 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\nf10_arp_reply_tb.sh 195 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\nf10_arp_reply_tb.v 3711 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\hdl\verilog\small_fifo_v3.v 2587 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_arp_reply_v1_00_a\Makefile 1333 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\data\nf10_axilite_rbs_bridge_v2_1_0.mpd 4730 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\data\nf10_axilite_rbs_bridge_v2_1_0.pao 1527 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\nf10_axilite_rbs_bridge_tb.prj 1597 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\nf10_axilite_rbs_bridge_tb.sh 1705 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\nf10_axilite_rbs_bridge_tb.tcl 1769 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\verilog\ipif_rbs_bridge.v 4893 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\verilog\nf10_axilite_rbs_bridge_tb.v 4744 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\verilog\udp_reg_master.v 6680 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\hdl\vhdl\nf10_axilite_rbs_bridge.vhd 15244 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\Makefile 1356 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axilite_rbs_bridge_v1_00_a\README 501 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\data\nf10_axis_memcached_client_v2_1_0.bbd 96 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\data\nf10_axis_memcached_client_v2_1_0.mpd 4964 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\data\nf10_axis_memcached_client_v2_1_0.mui 1994 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\data\nf10_axis_memcached_client_v2_1_0.pao 1531 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\verilog\axi4_lite_regs_memcached_client.v 18399 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\verilog\nf10_axis_memcached_streambuffer.v 1307 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\vhdl\nf10_axis_memcached_client.vhd 22513 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\vhdl\nf10_axis_memcached_client_tb.prj 709 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\vhdl\nf10_axis_memcached_client_tb.sh 277 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\vhdl\nf10_axis_memcached_client_tb.tcl 1511 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\hdl\vhdl\nf10_axis_memcached_client_tb.vhd 4573 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\Makefile 2354 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\netlist\icon_v5.ngc 37299 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\netlist\ila256_v5.ngc 1149943 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\netlist\vio_sync64_v5.ngc 98401 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\xco\async_fifo_1_16.xco 7010 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_memcached_client_v1_00_a\xco\async_fifo_32_129.xco 7016 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\data\nf10_axis_pbs_bridge_v2_1_0.mpd 4049 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\data\nf10_axis_pbs_bridge_v2_1_0.pao 1521 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\axis_pbs_bridge.v 7214 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\nf10_axis_pbs_bridge.v 6623 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\nf10_axis_pbs_bridge_tb.prj 1605 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\nf10_axis_pbs_bridge_tb.sh 1755 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\nf10_axis_pbs_bridge_tb.tcl 1854 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\nf10_axis_pbs_bridge_tb.v 7503 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\hdl\verilog\pbs_axis_bridge.v 7238 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_axis_pbs_bridge_v1_00_a\Makefile 1366 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\data\nf10_decap_v2_1_0.mpd 4771 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\data\nf10_decap_v2_1_0.pao 1443 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\decap_decision_maker.v 5477 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\fallthrough_small_fifo_v2.v 3291 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\nf10_decap.v 12757 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\nf10_decap_tb.prj 178 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\nf10_decap_tb.sh 183 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\nf10_decap_tb.v 4466 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\hdl\verilog\small_fifo_v3.v 2587 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_decap_v1_00_a\Makefile 1329 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\data\nf10_encap_v2_1_0.mpd 4771 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\data\nf10_encap_v2_1_0.pao 1434 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\encap_header_lookup.v 18832 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\fallthrough_small_fifo_v2.v 3291 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\nf10_encap.v 10025 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\nf10_encap_tb.prj 177 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\nf10_encap_tb.sh 183 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\nf10_encap_tb.v 3947 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\hdl\verilog\small_fifo_v3.v 2587 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_encap_v1_00_a\Makefile 1329 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_endianess_manager_v1_00_a\data\nf10_endianess_manager_v2_1_0.mpd 4353 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_endianess_manager_v1_00_a\data\nf10_endianess_manager_v2_1_0.pao 1363 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_endianess_manager_v1_00_a\hdl\verilog\bridge.v 3091 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_endianess_manager_v1_00_a\hdl\verilog\nf10_endianess_manager.v 5064 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\DelayAssy.bsv 18563 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp.bsv 10275 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp1001.bsv 2978 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_assy.bsv 1794 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_scenario0.bsv 3004 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_scenario1.bsv 2766 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_scenario2.bsv 2648 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_scenario3a.bsv 3362 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_scenario3b.bsv 3590 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\OCApp_scenario4.bsv 2649 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\app\README 553 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\axi\A4LS.bsv 2665 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\axi\ARAXI.bsv 286 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\axi\ARAXI4L.bsv 16583 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\axi\ARAXI4S.bsv 7664 2016-10-21
NetFPGA-1G-CML\lib\hw\contrib\pcores\nf10_oped_v1_10_a\bsv\axi\AXISDWorker.bsv 7339 2016-10-21
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