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xst_vlog_bl2cl25

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-01
  • Size : 215kb
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  • Author :happ*****
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xilinx ddr control xst
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FilenameSizeUpdate
xst_vlog_bl2cl25 0 2018-03-30
xst_vlog_bl2cl25\datasheet.txt 1291 2007-06-25
xst_vlog_bl2cl25\ddr.cpj 19111 2007-04-09
xst_vlog_bl2cl25\par 0 2018-03-30
xst_vlog_bl2cl25\par\ddr.cdc 12543 2007-03-12
xst_vlog_bl2cl25\par\mem_interface_top.bit 283860 2007-06-28
xst_vlog_bl2cl25\par\mem_interface_top.ucf 36142 2007-06-22
xst_vlog_bl2cl25\par\Readme.txt 657 2007-04-10
xst_vlog_bl2cl25\par\test.ise 353821 2007-06-22
xst_vlog_bl2cl25\Readme.txt 4086 2007-06-22
xst_vlog_bl2cl25\rtl 0 2018-03-30
xst_vlog_bl2cl25\rtl\mem_interface_top.v 3087 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_addr_gen_0.v 4554 2007-06-28
xst_vlog_bl2cl25\rtl\mem_interface_top_cal_ctl_0.v 4417 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_cal_top.v 1482 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_clk_dcm.v 2360 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_cmd_fsm_0.v 5670 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_cmp_data_0.v 3286 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_controller_0.v 44313 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_controller_iobs_0.v 7265 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_data_path_0.v 5999 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_data_path_iobs_0.v 8447 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_data_path_rst.v 1154 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_data_read_0.v 7211 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_data_read_controller_0.v 9449 2007-06-28
xst_vlog_bl2cl25\rtl\mem_interface_top_data_write_0.v 5320 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_ddr1_dm_0.v 2242 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_ddr1_test_bench_0.v 7398 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_dqs_delay.v 1907 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_fifo_0_wr_en_0.v 1431 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_fifo_1_wr_en_0.v 1565 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_infrastructure.v 1564 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_infrastructure_iobs_0.v 2256 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_infrastructure_top_0.v 5580 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_iobs_0.v 4754 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_lfsr32_0.v 2419 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_main_0.v 5944 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_parameters_0.v 3358 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_RAM8D_0.v 3725 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_RAM8D_1.v 3725 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_rd_gray_cntr.v 2477 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_s3_ddr_iob.v 2454 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_s3_dqs_iob.v 2482 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_tap_dly_0.v 10345 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_top_0.v 9592 2007-06-22
xst_vlog_bl2cl25\rtl\mem_interface_top_wr_gray_cntr.v 2403 2007-06-22
xst_vlog_bl2cl25\sim 0 2018-03-30
xst_vlog_bl2cl25\sim\ddr.v 57010 2007-06-22
xst_vlog_bl2cl25\sim\ddr1_test_tb.v 4829 2007-06-22
xst_vlog_bl2cl25\sim\ddr_parameters.vh 4372 2007-06-22
xst_vlog_bl2cl25\sim\glbl.v 1398 2007-06-22
xst_vlog_bl2cl25\sim\parameters.v 3360 2007-06-22
xst_vlog_bl2cl25\sim\readme.txt 1838 2007-06-22
xst_vlog_bl2cl25\synth 0 2018-03-30
xst_vlog_bl2cl25\synth\mem_interface_top.lso 6 2007-06-22
xst_vlog_bl2cl25\synth\mem_interface_top.prj 1876 2007-06-22
xst_vlog_bl2cl25\synth\mem_interface_top.sdc 34 2007-06-22
xst_vlog_bl2cl25\synth\mem_interface_top.xcf 151 2007-06-22
xst_vlog_bl2cl25\synth\mem_interface_top_synp.sdc 2894 2007-06-22
xst_vlog_bl2cl25\synth\script_synp.tcl 3066 2007-06-22
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