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my_led_ip
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Category :
VHDL-FPGA-Verilog
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Update : 2018-04-01
Size : 9kb
Downloaded :1次
Author :
ICwxf******
About : Nobody
PS : If download it fails, try it again. Download again for free!
Download1
Download2
Introduction - If you have any usage issues, please Google them yourself
Reedit
The four channel Axi LED lamp controller is used for some function instructions in the embedded system
Packet file list
(Preview for download)
Filename
Size
Update
my_led_ip\component.xml
10344
2018-03-20
my_led_ip\my_led_ip.cache\wt\gui_handlers.wdf
3172
2018-03-21
my_led_ip\my_led_ip.cache\wt\java_command_handlers.wdf
644
2018-03-21
my_led_ip\my_led_ip.cache\wt\project.wpc
61
2018-03-20
my_led_ip\my_led_ip.cache\wt\webtalk_pa.xml
3617
2018-03-21
my_led_ip\my_led_ip.hw\my_led_ip.lpr
290
2018-03-20
my_led_ip\my_led_ip.xpr
7031
2018-03-21
my_led_ip\src\my_led_ip.v
220
2018-03-20
my_led_ip\vivado.jou
4986
2018-03-21
my_led_ip\vivado.log
8694
2018-03-21
my_led_ip\xgui\my_led_ip_v1_0.tcl
205
2018-03-20
my_led_ip\my_led_ip.cache\compile_simlib\activehdl
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib\ies
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib\modelsim
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib\questa
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib\riviera
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib\vcs
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib\xcelium
0
2018-03-21
my_led_ip\my_led_ip.cache\ip\2017.4
0
2018-03-20
my_led_ip\.Xil\Vivado-18400-LAPTOP-PR3JV5P6_2
0
2018-03-21
my_led_ip\my_led_ip.cache\compile_simlib
0
2018-03-21
my_led_ip\my_led_ip.cache\ip
0
2018-03-20
my_led_ip\my_led_ip.cache\wt
0
2018-03-20
my_led_ip\.Xil
0
2018-03-21
my_led_ip\my_led_ip.cache
0
2018-03-21
my_led_ip\my_led_ip.hw
0
2018-03-21
my_led_ip\my_led_ip.ip_user_files
0
2018-03-21
my_led_ip\my_led_ip.sim
0
2018-03-21
my_led_ip\src
0
2018-03-24
my_led_ip\xgui
0
2018-03-20
my_led_ip
0
2018-04-01
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