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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-02
  • Size : 1.9mb
  • Downloaded :0次
  • Author :薇**
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Introduction - If you have any usage issues, please Google them yourself
The addition of IP core adder to the vivado platform developed by Xilinx is applied.
Packet file list
(Preview for download)
FilenameSizeUpdate
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try\try.cache\wt\webtalk_pa.xml 4593 2018-03-13
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try\try.ip_user_files\sim_scripts\c_addsub_0\riviera\compile.do 1497 2018-03-12
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try\try.ip_user_files\sim_scripts\c_addsub_0\riviera\README.txt 2186 2018-03-12
try\try.ip_user_files\sim_scripts\c_addsub_0\riviera\simulate.do 412 2018-03-12
try\try.ip_user_files\sim_scripts\c_addsub_0\riviera\wave.do 12 2018-03-12
try\try.ip_user_files\sim_scripts\c_addsub_0\vcs\c_addsub_0.sh 7656 2018-03-12
try\try.ip_user_files\sim_scripts\c_addsub_0\vcs\file_info.txt 848 2018-03-12
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try\try.ip_user_files\sim_scripts\c_addsub_0\xsim\cmd.tcl 464 2018-03-12
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try\try.ip_user_files\sim_scripts\c_addsub_0\xsim\elab.opt 300 2018-03-12
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try\try.ip_user_files\sim_scripts\c_addsub_0\xsim\vhdl.prj 103 2018-03-12
try\try.ip_user_files\sim_scripts\c_addsub_0\xsim\xsim.ini 19045 2017-12-16
try\try.runs\.jobs\vrs_config_1.xml 228 2018-03-12
try\try.runs\.jobs\vrs_config_2.xml 228 2018-03-12
try\try.runs\.jobs\vrs_config_3.xml 228 2018-03-12
try\try.runs\.jobs\vrs_config_4.xml 228 2018-03-12
try\try.runs\c_addsub_0_synth_1\.vivado.begin.rst 188 2018-03-12
try\try.runs\c_addsub_0_synth_1\.vivado.end.rst 0 2018-03-12
try\try.runs\c_addsub_0_synth_1\.Vivado_Synthesis.queue.rst 0 2018-03-12
try\try.runs\c_addsub_0_synth_1\c_addsub_0.dcp 23622 2018-03-12
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