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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-02
  • Size : 41.16mb
  • Downloaded :0次
  • Author :薇**
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
We use the vivado platform developed by Xilinx to realize the down conversion function.
Packet file list
(Preview for download)
FilenameSizeUpdate
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oo\oo.ip_user_files\mem_init_files\ddc_chbw5_C1_pb5_if0_frf153_os2_s4.mif 2147 2018-03-26
oo\oo.ip_user_files\mem_init_files\PWM.coe 1474536 2018-03-28
oo\oo.ip_user_files\mem_init_files\PWM_phase0.coe 331805 2018-03-28
oo\oo.ip_user_files\mem_init_files\rom16.mif 589788 2018-03-28
oo\oo.ip_user_files\mem_init_files\summary.log 904 2018-03-28
oo\oo.ip_user_files\README.txt 130 2018-03-21
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.mif 304095 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.sh 4899 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.udo 0 2018-03-28
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oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\file_info.txt 427 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\glbl.v 1474 2017-12-14
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oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\simulate.do 340 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\summary.log 904 2018-03-28
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oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.mif 304095 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.sh 5713 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\file_info.txt 427 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\glbl.v 1474 2017-12-14
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\PWM_phase0.coe 331805 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\README.txt 2142 2018-03-28
oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\run.f 487 2018-03-28
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