Code for the Verilog flow, such as the preparation procedures, have been compiled simulation quartuous6.0 passed, downloaded into the circuit board has been achieved

Packet : 71477227liushuideng.rar filelist
liushuideng\.sopc_builder\install.ptf
liushuideng\.sopc_builder
liushuideng\db\liushuideng.analyze_file.qmsg
liushuideng\db\liushuideng.cbx.xml
liushuideng\db\liushuideng.cmp.rdb
liushuideng\db\liushuideng.db_info
liushuideng\db\liushuideng.eco.cdb
liushuideng\db\liushuideng.hif
liushuideng\db\liushuideng.map.hdb
liushuideng\db\liushuideng.map.qmsg
liushuideng\db\liushuideng.sld_design_entry.sci
liushuideng\db\liushuideng.sld_design_entry_dsc.sci
liushuideng\db
liushuideng\liushuideng.done
liushuideng\liushuideng.flow.rpt
liushuideng\liushuideng.map.rpt
liushuideng\liushuideng.map.smsg
liushuideng\liushuideng.map.summary
liushuideng\liushuideng.qpf
liushuideng\liushuideng.qsf
liushuideng\liushuideng.qws
liushuideng\liushuideng.v
liushuideng\sopc_builder_debug_log.txt
liushuideng

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