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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-08
  • Size : 126kb
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  • Author :天天***
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Introduction - If you have any usage issues, please Google them yourself
74HC595 can turn serial signals into parallel signals, so they are usually used to drive various digital tubes and dot matrix screens.
Packet file list
(Preview for download)
FilenameSizeUpdate
0715_01_HC595\db 0 2018-04-01
0715_01_HC595\db\HC595.db_info 140 2018-04-01
0715_01_HC595\db\HC595.eco.cdb 164 2017-10-27
0715_01_HC595\db\HC595.ipinfo 163 2018-04-01
0715_01_HC595\db\HC595.sld_design_entry.sci 202 2018-04-01
0715_01_HC595\db\logic_util_heursitic.dat 2420 2017-09-03
0715_01_HC595\db\prev_cmp_HC595.qmsg 7095 2017-09-03
0715_01_HC595\dis.v 241 2017-09-03
0715_01_HC595\dis.v.bak 236 2017-09-03
0715_01_HC595\dis_top.v 395 2017-09-03
0715_01_HC595\dis_top_tb.v 414 2017-09-03
0715_01_HC595\dis_top_tb.v.bak 458 2017-09-03
0715_01_HC595\HC595.pti_db_list.ddb 217 2017-09-16
0715_01_HC595\HC595.qpf 1280 2017-09-03
0715_01_HC595\HC595.qsf 4508 2017-10-08
0715_01_HC595\HC595.qws 48 2018-04-01
0715_01_HC595\HC595.tis_db_list.ddb 235 2017-09-16
0715_01_HC595\HC595.v 2655 2017-09-03
0715_01_HC595\HC595.v.bak 2558 2017-09-03
0715_01_HC595\HC595_assignment_defaults.qdf 57451 2017-10-08
0715_01_HC595\HC595_nativelink_simulation.rpt 982 2017-09-03
0715_01_HC595\incremental_db 0 2018-03-01
0715_01_HC595\incremental_db\compiled_partitions 0 2018-03-01
0715_01_HC595\incremental_db\compiled_partitions\HC595.db_info 140 2017-10-08
0715_01_HC595\incremental_db\README 653 2017-09-03
0715_01_HC595\no_rev.pti_db_list.ddb 217 2017-10-27
0715_01_HC595\no_rev.tis_db_list.ddb 217 2017-10-27
0715_01_HC595\output_files 0 2018-03-01
0715_01_HC595\output_files\HC595.asm.rpt 7340 2017-09-03
0715_01_HC595\output_files\HC595.done 26 2017-09-03
0715_01_HC595\output_files\HC595.eda.rpt 7864 2017-09-03
0715_01_HC595\output_files\HC595.fit.rpt 130117 2017-09-03
0715_01_HC595\output_files\HC595.fit.smsg 703 2017-09-03
0715_01_HC595\output_files\HC595.fit.summary 611 2017-09-03
0715_01_HC595\output_files\HC595.flow.rpt 9717 2017-09-03
0715_01_HC595\output_files\HC595.jdi 224 2017-09-03
0715_01_HC595\output_files\HC595.map.rpt 23049 2017-09-03
0715_01_HC595\output_files\HC595.map.summary 465 2017-09-03
0715_01_HC595\output_files\HC595.pin 33077 2017-09-03
0715_01_HC595\output_files\HC595.sof 358644 2017-09-03
0715_01_HC595\output_files\HC595.sta.rpt 135780 2017-09-03
0715_01_HC595\output_files\HC595.sta.summary 948 2017-09-03
0715_01_HC595\simulation 0 2018-03-01
0715_01_HC595\simulation\modelsim 0 2018-03-01
0715_01_HC595\simulation\modelsim\HC595.sft 335 2017-09-03
0715_01_HC595\simulation\modelsim\HC595.vo 22427 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_8_1200mv_0c_slow.vo 22444 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_8_1200mv_0c_v_slow.sdo 18268 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_8_1200mv_85c_slow.vo 22445 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_8_1200mv_85c_v_slow.sdo 18272 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_min_1200mv_0c_fast.vo 22446 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_min_1200mv_0c_v_fast.sdo 17881 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_modelsim.xrf 2816 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_run_msim_rtl_verilog.do 894 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_run_msim_rtl_verilog.do.bak 894 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_run_msim_rtl_verilog.do.bak1 894 2017-09-03
0715_01_HC595\simulation\modelsim\HC595_v.sdo 18272 2017-09-03
0715_01_HC595\simulation\modelsim\modelsim.ini 11131 2017-09-03
0715_01_HC595\simulation\modelsim\msim_transcript 2737 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work 0 2018-03-01
0715_01_HC595\simulation\modelsim\rtl_work\@h@c595 0 2018-03-01
0715_01_HC595\simulation\modelsim\rtl_work\@h@c595\_primary.dat 2225 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\@h@c595\_primary.dbs 2627 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\@h@c595\_primary.vhd 663 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\@h@c595\verilog.prw 743 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\@h@c595\verilog.psm 23832 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\_info 2324 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\_temp 0 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\_vmake 26 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis 0 2018-03-01
0715_01_HC595\simulation\modelsim\rtl_work\dis\_primary.dat 316 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis\_primary.dbs 425 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis\_primary.vhd 292 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis\verilog.prw 169 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis\verilog.psm 2960 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top 0 2018-03-01
0715_01_HC595\simulation\modelsim\rtl_work\dis_top\_primary.dat 564 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top\_primary.dbs 772 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top\_primary.vhd 305 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top\verilog.prw 169 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top\verilog.psm 4664 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top_tb 0 2018-03-01
0715_01_HC595\simulation\modelsim\rtl_work\dis_top_tb\_primary.dat 518 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top_tb\_primary.dbs 1054 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top_tb\_primary.vhd 80 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top_tb\verilog.prw 443 2017-09-03
0715_01_HC595\simulation\modelsim\rtl_work\dis_top_tb\verilog.psm 5168 2017-09-03
0715_01_HC595\simulation\modelsim\vsim.wlf 81920 2017-09-03
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