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uart_55x_lite

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2018-04-09
  • Size : 35kb
  • Downloaded :0次
  • Author :fengy******
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The module is designed and modeled on ST16C554 chip. A) Localbus bus interface; B) multi-channel design. The maximum number of channels is 4, and the number of actual channels is configurable. C) two interrupt modes, supporting level interruption and interruption.
Packet file list
(Preview for download)
FilenameSizeUpdate
uart_55x_lite 0 2016-06-14
uart_55x_lite\greybox_tmp 0 2016-06-14
uart_55x_lite\greybox_tmp\cbx_args.txt 482 2015-04-15
uart_55x_lite\pll_30m_in.qip 0 2015-04-15
uart_55x_lite\sdpram_dxw8.qip 0 2015-04-15
uart_55x_lite\uart_55x_lite.v 23054 2016-06-13
uart_55x_lite\uart_55x_lite.v.bak 23048 2016-05-06
uart_55x_lite\uart_baud_gen.v 3035 2014-09-02
uart_55x_lite\uart_channel.v 20075 2016-06-28
uart_55x_lite\uart_channel.v.bak 20073 2015-04-27
uart_55x_lite\uart_driver.v 6649 2014-02-19
uart_55x_lite\uart_fifoarbiter.v 13074 2014-02-19
uart_55x_lite\uart_intc.v 6240 2014-02-19
uart_55x_lite\uart_receive.v 15075 2016-06-26
uart_55x_lite\uart_regs.v 32734 2016-06-28
uart_55x_lite\uart_regs.v.bak 32697 2014-09-28
uart_55x_lite\uart_rxfifo_if.v 17450 2014-09-02
uart_55x_lite\uart_send.v 9863 2014-02-18
uart_55x_lite\uart_txfifo_if.v 20345 2014-09-02
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