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C5G_SRAM_RTL_Test

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-10
  • Size : 476kb
  • Downloaded :0次
  • Author :橙子***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The SRAM project of official website C5 board can be used directly
Packet file list
(Preview for download)
FilenameSizeUpdate
C5G_SRAM_RTL_Test 0 2015-03-19
C5G_SRAM_RTL_Test\.qsys_edit 0 2015-03-19
C5G_SRAM_RTL_Test\.qsys_edit\filters.xml 68 2013-07-24
C5G_SRAM_RTL_Test\.qsys_edit\preferences.xml 493 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.cdf 354 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.done 26 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.dpf 1193 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.fit.smsg 482 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.fit.summary 716 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.jdi 4911 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.map.smsg 84 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.map.summary 543 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.pin 79596 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.qpf 116 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.qsf 81042 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.qws 1455 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.sdc 2568 2014-06-23
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.sof 4001966 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.sta.summary 5981 2014-05-15
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test.v 8272 2013-07-24
C5G_SRAM_RTL_Test\C5G_SRAM_RTL_Test_assignment_defaults.qdf 47533 2014-05-15
C5G_SRAM_RTL_Test\c5_pin_model_dump.txt 3697 2013-07-24
C5G_SRAM_RTL_Test\demo_batch 0 2015-03-19
C5G_SRAM_RTL_Test\demo_batch\C5G_SRAM_RTL_Test.bat 430 2013-07-24
C5G_SRAM_RTL_Test\demo_batch\C5G_SRAM_RTL_Test.sof 4001966 2014-05-15
C5G_SRAM_RTL_Test\hc_output 0 2015-03-19
C5G_SRAM_RTL_Test\hc_output\C5G_SRAM_RTL_Test.names_drv_tbl 420272 2013-07-24
C5G_SRAM_RTL_Test\pll.xml 9719 2014-05-15
C5G_SRAM_RTL_Test\PLLJ_PLLSPE_INFO.txt 285 2013-07-24
C5G_SRAM_RTL_Test\stp1.stp 389819 2013-07-24
C5G_SRAM_RTL_Test\stp1_auto_stripped.stp 389819 2013-07-24
C5G_SRAM_RTL_Test\v 0 2015-03-19
C5G_SRAM_RTL_Test\v\Avalon_bus_RW_Test.v 4937 2013-07-24
C5G_SRAM_RTL_Test\v\fpga_sram.v 1147 2013-07-24
C5G_SRAM_RTL_Test\v\pll 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll.bsf 3446 2013-07-24
C5G_SRAM_RTL_Test\v\pll.cmp 233 2013-07-24
C5G_SRAM_RTL_Test\v\pll.ppf 424 2013-07-24
C5G_SRAM_RTL_Test\v\pll.qip 950 2014-05-15
C5G_SRAM_RTL_Test\v\pll.sip 459 2014-05-15
C5G_SRAM_RTL_Test\v\pll.spd 172 2013-07-24
C5G_SRAM_RTL_Test\v\pll.v 17477 2014-05-15
C5G_SRAM_RTL_Test\v\pll\pll_0002.qip 298 2013-07-24
C5G_SRAM_RTL_Test\v\pll\pll_0002.v 2156 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim.f 15 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim\aldec 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim\aldec\rivierapro_setup.tcl 7407 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim\cadence 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim\cadence\cds.lib 1297 2013-07-24
C5G_SRAM_RTL_Test\v\pll_sim\cadence\hdl.var 18 2013-07-24
C5G_SRAM_RTL_Test\v\pll_sim\cadence\ncsim_setup.sh 4362 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim\mentor 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim\mentor\msim_setup.tcl 7132 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim\pll.vo 15062 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim\synopsys 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim\synopsys\vcs 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim\synopsys\vcsmx 0 2015-03-19
C5G_SRAM_RTL_Test\v\pll_sim\synopsys\vcsmx\synopsys_sim.setup 616 2013-07-24
C5G_SRAM_RTL_Test\v\pll_sim\synopsys\vcsmx\vcsmx_setup.sh 4439 2014-05-15
C5G_SRAM_RTL_Test\v\pll_sim\synopsys\vcs\vcs_setup.sh 2948 2014-05-15
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