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ug871-design-files

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  • Update : 2018-04-11
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XILINX FPGA PCIE test routine
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FilenameSizeUpdate
ug871-design-files 0 2016-11-01
ug871-design-files\Arbitrary_Precision 0 2016-11-01
ug871-design-files\Arbitrary_Precision\lab1 0 2016-11-01
ug871-design-files\Arbitrary_Precision\lab1\run_hls.tcl 3304 2013-03-08
ug871-design-files\Arbitrary_Precision\lab1\window_fn_class.h 5211 2013-03-08
ug871-design-files\Arbitrary_Precision\lab1\window_fn_test.cpp 4287 2013-03-08
ug871-design-files\Arbitrary_Precision\lab1\window_fn_top.cpp 3383 2015-09-11
ug871-design-files\Arbitrary_Precision\lab1\window_fn_top.h 3087 2013-03-08
ug871-design-files\Arbitrary_Precision\lab2 0 2016-11-01
ug871-design-files\Arbitrary_Precision\lab2\run_hls.tcl 3304 2013-03-08
ug871-design-files\Arbitrary_Precision\lab2\window_fn_class.h 5222 2013-03-04
ug871-design-files\Arbitrary_Precision\lab2\window_fn_test.cpp 4287 2013-03-08
ug871-design-files\Arbitrary_Precision\lab2\window_fn_top.cpp 3383 2016-03-24
ug871-design-files\Arbitrary_Precision\lab2\window_fn_top.h 3283 2013-03-04
ug871-design-files\C_Validation 0 2016-11-01
ug871-design-files\C_Validation\lab1 0 2016-11-01
ug871-design-files\C_Validation\lab1\hamming_window.c 3784 2013-12-14
ug871-design-files\C_Validation\lab1\hamming_window.h 3478 2013-03-08
ug871-design-files\C_Validation\lab1\hamming_window_test.c 4307 2013-03-08
ug871-design-files\C_Validation\lab1\run_hls.tcl 3312 2013-03-08
ug871-design-files\C_Validation\lab2 0 2016-11-01
ug871-design-files\C_Validation\lab2\hamming_window.c 3705 2016-03-23
ug871-design-files\C_Validation\lab2\hamming_window.h 3556 2013-03-08
ug871-design-files\C_Validation\lab2\hamming_window_test.c 4397 2016-03-23
ug871-design-files\C_Validation\lab2\run_hls.tcl 3312 2013-03-08
ug871-design-files\C_Validation\lab3 0 2016-11-01
ug871-design-files\C_Validation\lab3\hamming_window.cpp 3707 2016-03-23
ug871-design-files\C_Validation\lab3\hamming_window.h 3642 2013-03-08
ug871-design-files\C_Validation\lab3\hamming_window_test.cpp 4203 2013-03-08
ug871-design-files\C_Validation\lab3\run_hls.tcl 3316 2013-03-08
ug871-design-files\Design_Analysis 0 2016-11-01
ug871-design-files\Design_Analysis\lab1 0 2016-11-01
ug871-design-files\Design_Analysis\lab1\dct.cpp 4677 2016-03-24
ug871-design-files\Design_Analysis\lab1\dct.h 429 2012-09-27
ug871-design-files\Design_Analysis\lab1\dct_coeff_table.txt 455 2011-07-09
ug871-design-files\Design_Analysis\lab1\dct_test.cpp 821 2012-09-27
ug871-design-files\Design_Analysis\lab1\in.dat 13595 2011-07-09
ug871-design-files\Design_Analysis\lab1\out.golden.dat 450 2012-09-27
ug871-design-files\Design_Analysis\lab1\run_hls.tcl 3322 2013-02-28
ug871-design-files\Design_Optimization 0 2016-11-01
ug871-design-files\Design_Optimization\lab1 0 2016-11-01
ug871-design-files\Design_Optimization\lab1\matrixmul.cpp 3117 2016-03-25
ug871-design-files\Design_Optimization\lab1\matrixmul.h 3080 2013-03-09
ug871-design-files\Design_Optimization\lab1\matrixmul_test.cpp 3964 2013-03-09
ug871-design-files\Design_Optimization\lab1\run_hls.tcl 3302 2013-03-09
ug871-design-files\Design_Optimization\lab2 0 2016-11-01
ug871-design-files\Design_Optimization\lab2\matrixmul.cpp 3793 2015-09-12
ug871-design-files\Design_Optimization\lab2\matrixmul.h 3080 2013-03-09
ug871-design-files\Design_Optimization\lab2\matrixmul_test.cpp 3963 2013-03-11
ug871-design-files\Design_Optimization\lab2\run_hls.tcl 3302 2013-03-29
ug871-design-files\Interface_Synthesis 0 2016-11-01
ug871-design-files\Interface_Synthesis\lab1 0 2016-11-01
ug871-design-files\Interface_Synthesis\lab1\adders.c 2874 2016-04-12
ug871-design-files\Interface_Synthesis\lab1\adders.h 2680 2013-01-25
ug871-design-files\Interface_Synthesis\lab1\adders_test.c 3309 2013-12-14
ug871-design-files\Interface_Synthesis\lab1\run_hls.tcl 3281 2016-03-23
ug871-design-files\Interface_Synthesis\lab2 0 2016-11-01
ug871-design-files\Interface_Synthesis\lab2\adders_io.c 2671 2016-03-24
ug871-design-files\Interface_Synthesis\lab2\adders_io.h 2698 2013-01-26
ug871-design-files\Interface_Synthesis\lab2\adders_io_test.c 3353 2013-01-26
ug871-design-files\Interface_Synthesis\lab2\run_hls.tcl 3290 2013-03-28
ug871-design-files\Interface_Synthesis\lab3 0 2016-11-01
ug871-design-files\Interface_Synthesis\lab3\array_io.c 3330 2016-03-24
ug871-design-files\Interface_Synthesis\lab3\array_io.h 2854 2013-01-26
ug871-design-files\Interface_Synthesis\lab3\array_io_test.c 3445 2013-01-26
ug871-design-files\Interface_Synthesis\lab3\result.golden.dat 313 2013-01-26
ug871-design-files\Interface_Synthesis\lab3\run_hls.tcl 3319 2013-01-26
ug871-design-files\Interface_Synthesis\lab4 0 2016-11-01
ug871-design-files\Interface_Synthesis\lab4\axi_interfaces.c 3319 2016-03-24
ug871-design-files\Interface_Synthesis\lab4\axi_interfaces.h 2878 2013-02-01
ug871-design-files\Interface_Synthesis\lab4\axi_interfaces_test.c 3463 2013-02-01
ug871-design-files\Interface_Synthesis\lab4\result.golden.dat 313 2013-01-26
ug871-design-files\Interface_Synthesis\lab4\run_hls.tcl 3343 2013-02-01
ug871-design-files\Introduction 0 2016-11-01
ug871-design-files\Introduction\lab1 0 2016-11-01
ug871-design-files\Introduction\lab1\fir.c 2902 2015-09-04
ug871-design-files\Introduction\lab1\fir.h 2767 2013-03-22
ug871-design-files\Introduction\lab1\fir_test.c 3870 2014-04-04
ug871-design-files\Introduction\lab1\out.gold.dat 7728 2012-04-12
ug871-design-files\Introduction\lab2 0 2016-11-01
ug871-design-files\Introduction\lab2\fir.c 2903 2015-09-04
ug871-design-files\Introduction\lab2\fir.h 2767 2013-03-22
ug871-design-files\Introduction\lab2\fir_test.c 3871 2013-03-22
ug871-design-files\Introduction\lab2\out.gold.dat 7728 2012-04-12
ug871-design-files\Introduction\lab2\run_hls.txt 768 2015-07-21
ug871-design-files\Introduction\lab3 0 2016-11-01
ug871-design-files\Introduction\lab3\fir.c 2902 2016-04-12
ug871-design-files\Introduction\lab3\fir.h 2767 2013-03-22
ug871-design-files\Introduction\lab3\fir_test.c 3871 2013-03-22
ug871-design-files\Introduction\lab3\out.gold.dat 7728 2012-04-12
ug871-design-files\Introduction\lab3\run_hls.tcl 698 2013-03-26
ug871-design-files\RTL_Verification 0 2016-11-01
ug871-design-files\RTL_Verification\lab1 0 2016-11-01
ug871-design-files\RTL_Verification\lab1\dds.c 631 2010-06-25
ug871-design-files\RTL_Verification\lab1\dds.dat 1152 2010-06-25
ug871-design-files\RTL_Verification\lab1\dds_table.h 251 2010-06-25
ug871-design-files\RTL_Verification\lab1\duc.c 808 2014-04-10
ug871-design-files\RTL_Verification\lab1\duc.h 2193 2013-03-07
ug871-design-files\RTL_Verification\lab1\duc_test.c 1543 2016-03-25
ug871-design-files\RTL_Verification\lab1\golden 0 2016-11-01
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