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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-12
  • Size : 509kb
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  • Author :呵*****
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The ten bit adder counter program requires 0-9 to count from 2.experimental design
Packet file list
(Preview for download)
FilenameSizeUpdate
three\bate.v 1178 2018-03-28
three\bate.v.bak 1165 2018-03-28
three\db\logic_util_heursitic.dat 0 2018-04-10
three\db\prev_cmp_three.qmsg 197 2018-04-10
three\db\three.(0).cnf.cdb 3703 2018-03-28
three\db\three.(0).cnf.hdb 2211 2018-03-28
three\db\three.asm.qmsg 2477 2018-03-28
three\db\three.asm.rdb 1471 2018-03-28
three\db\three.cbx.xml 87 2018-04-10
three\db\three.cmp.idb 4053 2018-03-28
three\db\three.cmp.kpt 203 2018-03-28
three\db\three.cmp.rdb 5972 2018-04-10
three\db\three.cmp0.ddb 62060 2018-03-28
three\db\three.cmp1.ddb 61402 2018-03-28
three\db\three.cmp2.ddb 43053 2018-03-28
three\db\three.cmp_merge.kpt 207 2018-04-10
three\db\three.db_info 140 2018-04-10
three\db\three.eda.qmsg 2551 2018-03-28
three\db\three.fit.qmsg 32053 2018-03-28
three\db\three.hier_info 1154 2018-04-10
three\db\three.hif 420 2018-04-10
three\db\three.ipinfo 163 2018-04-10
three\db\three.lpc.html 372 2018-04-10
three\db\three.lpc.rdb 399 2018-04-10
three\db\three.lpc.txt 1060 2018-04-10
three\db\three.map.ammdb 123 2018-04-10
three\db\three.map.bpm 557 2018-04-10
three\db\three.map.cdb 4373 2018-04-10
three\db\three.map.hdb 11714 2018-04-10
three\db\three.map.kpt 497 2018-04-10
three\db\three.map.logdb 4 2018-04-10
three\db\three.map.qmsg 14878 2018-04-10
three\db\three.map.rdb 1307 2018-04-10
three\db\three.map_bb.cdb 1781 2018-04-10
three\db\three.map_bb.hdb 9681 2018-04-10
three\db\three.map_bb.logdb 4 2018-04-10
three\db\three.pplq.rdb 232 2018-03-28
three\db\three.pre_map.hdb 11375 2018-04-10
three\db\three.pti_db_list.ddb 177 2018-04-10
three\db\three.root_partition.map.reg_db.cdb 196 2018-04-10
three\db\three.routing.rdb 2909 2018-03-28
three\db\three.rtlv.hdb 11304 2018-04-10
three\db\three.rtlv_sg.cdb 3459 2018-04-10
three\db\three.rtlv_sg_swap.cdb 181 2018-04-10
three\db\three.sgdiff.cdb 4302 2018-04-10
three\db\three.sgdiff.hdb 11530 2018-04-10
three\db\three.sld_design_entry.sci 202 2018-04-10
three\db\three.sld_design_entry_dsc.sci 202 2018-04-10
three\db\three.smart_action.txt 5 2018-04-10
three\db\three.sta.qmsg 17888 2018-03-28
three\db\three.sta.rdb 16804 2018-03-28
three\db\three.syn_hier_info 0 2018-04-10
three\db\three.tis_db_list.ddb 177 2018-04-10
three\db\three.tmw_info 113 2018-04-10
three\db\three.vpr.ammdb 306 2018-03-28
three\incremental_db\compiled_partitions\three.db_info 140 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.ammdb 307 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.cdb 5557 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.dfp 33 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.hdb 11293 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.kpt 205 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.logdb 4 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.cmp.rcfdb 3696 2018-03-28
three\incremental_db\compiled_partitions\three.root_partition.map.cdb 4436 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.dpi 652 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.hbdb.cdb 1288 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.hbdb.hb_info 46 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.hbdb.hdb 11371 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.hbdb.sig 32 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.hdb 11664 2018-04-10
three\incremental_db\compiled_partitions\three.root_partition.map.kpt 501 2018-04-10
three\incremental_db\README 653 2018-03-28
three\OurFPGA.tcl 1244 2018-03-28
three\output_files\three.asm.rpt 7446 2018-03-28
three\output_files\three.done 26 2018-04-10
three\output_files\three.eda.rpt 5849 2018-03-28
three\output_files\three.fit.rpt 99667 2018-03-28
three\output_files\three.fit.smsg 703 2018-03-28
three\output_files\three.fit.summary 601 2018-03-28
three\output_files\three.flow.rpt 8350 2018-04-10
three\output_files\three.jdi 223 2018-03-28
three\output_files\three.map.rpt 25776 2018-04-10
three\output_files\three.map.summary 459 2018-04-10
three\output_files\three.pin 27097 2018-03-28
three\output_files\three.pof 524494 2018-03-28
three\output_files\three.sof 241101 2018-03-28
three\output_files\three.sta.rpt 112596 2018-03-28
three\output_files\three.sta.summary 2158 2018-03-28
three\simulation\modelsim\modelsim.ini 11131 2018-04-10
three\simulation\modelsim\msim_transcript 1442 2018-04-10
three\simulation\modelsim\rtl_work\bate\verilog.prw 651 2018-04-10
three\simulation\modelsim\rtl_work\bate\verilog.psm 11760 2018-04-10
three\simulation\modelsim\rtl_work\bate\_primary.dat 1444 2018-04-10
three\simulation\modelsim\rtl_work\bate\_primary.dbs 1537 2018-04-10
three\simulation\modelsim\rtl_work\bate\_primary.vhd 275 2018-04-10
three\simulation\modelsim\rtl_work\test\verilog.prw 413 2018-04-10
three\simulation\modelsim\rtl_work\test\verilog.psm 4920 2018-04-10
three\simulation\modelsim\rtl_work\test\_primary.dat 424 2018-04-10
three\simulation\modelsim\rtl_work\test\_primary.dbs 702 2018-04-10
three\simulation\modelsim\rtl_work\test\_primary.vhd 68 2018-04-10
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