A digital clock module written by Verilog HDL, including timing function, debugging and downloading through Maxplusii.

Filename	Size	Update
clk_gen.v	790	2005-11-05
count6.v	532	2005-11-07
count10.v	537	2005-11-07
pp2.v	165	2005-11-05
top.v	3723	2005-11-07
top_tf.v	2068	2005-11-05
top.scf	27270	2005-11-05

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