Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

DDR3_A4

FavoriteReport
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2018-04-13
  • Size : 23.23mb
  • Downloaded ：0次
  • Author ：amz***
  • About ： Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Introduction - If you have any usage issues, please Google them yourself
DEMO routines driven by Xilinx FPGA A7 for DDR3
Packet file list
(Preview for download)
FilenameSizeUpdate
DDR3_A4\.Xil\Vivado-9512-LAPTOP-HB6EUDTQ\hw_ila_data_1\xsim.dir\snapshot\xsim.dbg 3496 2016-11-17
DDR3_A4\.Xil\Vivado-9512-LAPTOP-HB6EUDTQ\hw_ila_data_1\xsim.dir\snapshot\xsim.rtti 1125 2016-11-17
DDR3_A4\DDR3.cache\ip\5363ae41685ecd6c\5363ae41685ecd6c.xci 268798 2016-06-07
DDR3_A4\DDR3.cache\ip\5363ae41685ecd6c\u_ila_0_0_CV.dcp 1890478 2016-06-07
DDR3_A4\DDR3.cache\ip\892c10722b89e868\892c10722b89e868.xci 6213 2016-06-07
DDR3_A4\DDR3.cache\ip\892c10722b89e868\dbg_hub_CV.dcp 210097 2016-06-07
DDR3_A4\DDR3.cache\ip\d258f8d21c5bf1c7\d258f8d21c5bf1c7.xci 268798 2016-06-07
DDR3_A4\DDR3.cache\ip\d258f8d21c5bf1c7\u_ila_0_0_CV.dcp 1889364 2016-06-07
DDR3_A4\DDR3.cache\wt\java_command_handlers.wdf 286 2017-01-18
DDR3_A4\DDR3.cache\wt\synthesis.wdf 3739 2016-11-17
DDR3_A4\DDR3.cache\wt\synthesis_details.wdf 100 2016-11-17
DDR3_A4\DDR3.cache\wt\webtalk_pa.xml 1485 2017-01-18
DDR3_A4\DDR3.hw\DDR3.lpr 343 2016-06-07
DDR3_A4\DDR3.hw\hw_1\hw.xml 38545 2017-03-08
DDR3_A4\DDR3.hw\hw_1\layout\hw_ila_1.layout 246910 2016-11-17
DDR3_A4\DDR3.hw\hw_1\wave\hw_ila_data_1\hw_ila_data_1.wcfg 9106 2016-06-07
DDR3_A4\DDR3.hw\hw_1\wave\hw_ila_data_1\hw_ila_data_1.wdb 7110 2016-11-17
DDR3_A4\DDR3.hw\webtalk\.xsim_webtallk.info 60 2017-01-18
DDR3_A4\DDR3.hw\webtalk\labtool_webtalk.log 636 2017-01-17
DDR3_A4\DDR3.hw\webtalk\labtool_webtalk.tcl 3260 2017-01-18
DDR3_A4\DDR3.hw\webtalk\usage_statistics_ext_labtool.html 2964 2017-01-17
DDR3_A4\DDR3.hw\webtalk\usage_statistics_ext_labtool.wdm 1138 2017-01-18
DDR3_A4\DDR3.hw\webtalk\usage_statistics_ext_labtool.xml 2566 2017-01-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_1.xml 202 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_10.xml 451 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_11.xml 451 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_12.xml 260 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_13.xml 695 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_14.xml 260 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_15.xml 695 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_2.xml 219 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_3.xml 202 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_4.xml 202 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_5.xml 219 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_6.xml 391 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_7.xml 219 2016-06-07
DDR3_A4\DDR3.runs\.jobs\vrs_config_8.xml 695 2016-11-17
DDR3_A4\DDR3.runs\.jobs\vrs_config_9.xml 451 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.init_design.begin.rst 183 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.init_design.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.opt_design.begin.rst 183 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.opt_design.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.place_design.begin.rst 183 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.place_design.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.route_design.begin.rst 183 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.route_design.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.vivado.begin.rst 182 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.vivado.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.Vivado_Implementation.queue.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.write_bitstream.begin.rst 183 2016-11-17
DDR3_A4\DDR3.runs\impl_1\.write_bitstream.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3.bit 3825889 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3.mcs 10761048 2016-06-07
DDR3_A4\DDR3.runs\impl_1\DDR3.tcl 5545 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3.vdi 28518 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_clock_utilization_routed.rpt 66937 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_control_sets_placed.rpt 220608 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_drc_opted.rpt 2154 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_drc_routed.pb 37 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_drc_routed.rpt 7682 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_io_placed.rpt 123484 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_opt.dcp 2888601 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_placed.dcp 4246986 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_power_routed.rpt 79350 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_power_summary_routed.pb 676 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_routed.dcp 5500100 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_route_status.pb 44 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_route_status.rpt 651 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_timing_summary_routed.rpt 4686937 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_timing_summary_routed.rpx 4167733 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_utilization_placed.pb 231 2016-11-17
DDR3_A4\DDR3.runs\impl_1\DDR3_utilization_placed.rpt 12791 2016-11-17
DDR3_A4\DDR3.runs\impl_1\gen_run.xml 6408 2016-11-17
DDR3_A4\DDR3.runs\impl_1\htr.txt 377 2016-11-17
DDR3_A4\DDR3.runs\impl_1\init_design.pb 6022 2016-11-17
DDR3_A4\DDR3.runs\impl_1\ISEWrap.js 4766 2016-11-17
DDR3_A4\DDR3.runs\impl_1\ISEWrap.sh 1622 2016-11-17
DDR3_A4\DDR3.runs\impl_1\opt_design.pb 6734 2016-11-17
DDR3_A4\DDR3.runs\impl_1\place_design.pb 17441 2016-11-17
DDR3_A4\DDR3.runs\impl_1\project.wdf 1838 2016-11-17
DDR3_A4\DDR3.runs\impl_1\route_design.pb 12108 2016-11-17
DDR3_A4\DDR3.runs\impl_1\rundef.js 1416 2016-11-17
DDR3_A4\DDR3.runs\impl_1\runme.bat 229 2016-11-17
DDR3_A4\DDR3.runs\impl_1\runme.log 28895 2016-11-17
DDR3_A4\DDR3.runs\impl_1\runme.sh 1238 2016-11-17
DDR3_A4\DDR3.runs\impl_1\vivado.jou 529 2016-11-17
DDR3_A4\DDR3.runs\impl_1\vivado.pb 129 2016-11-17
DDR3_A4\DDR3.runs\impl_1\write_bitstream.pb 3232 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\.vivado.begin.rst 182 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\.vivado.end.rst 0 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\.Vivado_Synthesis.queue.rst 0 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\.Xil\mig_7series_0_propImpl.xdc 9214 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\fsm_encoding.os 2094 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\gen_run.xml 2091 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\htr.txt 387 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\ISEWrap.js 4766 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\ISEWrap.sh 1622 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\mig_7series_0.dcp 3069959 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\mig_7series_0.tcl 3525 2016-11-17
DDR3_A4\DDR3.runs\mig_7series_0_synth_1\mig_7series_0.vds 633478 2016-11-17
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information
Comment

Nothing．

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content ：
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.