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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-13
  • Size : 54kb
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  • Author :amz***
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Introduction - If you have any usage issues, please Google them yourself
Xilinx FPGA read and write EEPROM routine
Packet file list
(Preview for download)
FilenameSizeUpdate
EEPROM\EEPROM.srcs\constrs_1\new\top_xdc.xdc 480 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1.dcp 10054 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1.v 3817 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1.veo 3529 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1.xci 70135 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1.xdc 2643 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1.xml 298984 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_board.xdc 60 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_clk_wiz.v 6344 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_funcsim.v 7595 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_funcsim.vhdl 8030 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_ooc.xdc 2482 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_stub.v 1197 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\clk_wiz_1_stub.vhdl 1162 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\doc\clk_wiz_v5_1_changelog.txt 4209 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\EEPROM.v 2474 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\fifo.v 2464 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\iic_ctr_top.v 11404 2017-09-30
EEPROM\EEPROM.srcs\sources_1\new\IIC_rdstate_ctr.v 4347 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\mode_m_counter.v 1112 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\scl.v 1282 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\sda_state.v 2370 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\shift8.v 509 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\uart_tx.v 2599 2016-06-07
EEPROM\EEPROM.srcs\sources_1\new\uart_tx_top.v 1923 2016-06-07
EEPROM\EEPROM.xpr 7102 2016-06-07
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1\doc 0 2017-09-30
EEPROM\EEPROM.srcs\sources_1\ip\clk_wiz_1 0 2017-09-30
EEPROM\EEPROM.srcs\constrs_1\new 0 2017-09-30
EEPROM\EEPROM.srcs\sources_1\ip 0 2017-09-30
EEPROM\EEPROM.srcs\sources_1\new 0 2017-09-30
EEPROM\EEPROM.srcs\constrs_1 0 2017-09-30
EEPROM\EEPROM.srcs\sources_1 0 2017-09-30
EEPROM\EEPROM.srcs 0 2017-09-30
EEPROM 0 2017-09-30
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