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  • Update : 2018-04-18
  • Size : 61kb
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Introduction - If you have any usage issues, please Google them yourself
Verilog code implements data flow input detection and integrated simulation.
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FilenameSizeUpdate
Flow\Flow.cache\wt\java_command_handlers.wdf 154 2018-04-18
Flow\Flow.cache\wt\project.wpc 61 2018-04-18
Flow\Flow.cache\wt\synthesis.wdf 3743 2018-04-18
Flow\Flow.cache\wt\synthesis_details.wdf 100 2018-04-18
Flow\Flow.cache\wt\webtalk_pa.xml 1416 2018-04-18
Flow\Flow.cache\wt\xsim.wdf 256 2018-04-18
Flow\Flow.hw\Flow.lpr 290 2018-04-17
Flow\Flow.ip_user_files\README.txt 130 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_1.xml 215 2018-04-17
Flow\Flow.runs\.jobs\vrs_config_10.xml 215 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_2.xml 215 2018-04-17
Flow\Flow.runs\.jobs\vrs_config_3.xml 215 2018-04-17
Flow\Flow.runs\.jobs\vrs_config_4.xml 215 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_5.xml 215 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_6.xml 215 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_7.xml 215 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_8.xml 215 2018-04-18
Flow\Flow.runs\.jobs\vrs_config_9.xml 215 2018-04-18
Flow\Flow.runs\synth_1\.vivado.begin.rst 188 2018-04-18
Flow\Flow.runs\synth_1\.vivado.end.rst 0 2018-04-18
Flow\Flow.runs\synth_1\.Vivado_Synthesis.queue.rst 0 2018-04-18
Flow\Flow.runs\synth_1\Flow.dcp 10341 2018-04-18
Flow\Flow.runs\synth_1\Flow.tcl 1079 2018-04-18
Flow\Flow.runs\synth_1\Flow.vds 16223 2018-04-18
Flow\Flow.runs\synth_1\Flow_utilization_synth.pb 249 2018-04-18
Flow\Flow.runs\synth_1\Flow_utilization_synth.rpt 7229 2018-04-18
Flow\Flow.runs\synth_1\gen_run.xml 1683 2018-04-18
Flow\Flow.runs\synth_1\htr.txt 369 2018-04-18
Flow\Flow.runs\synth_1\ISEWrap.js 7308 2018-04-18
Flow\Flow.runs\synth_1\ISEWrap.sh 1622 2018-04-18
Flow\Flow.runs\synth_1\project.wdf 1951 2018-04-18
Flow\Flow.runs\synth_1\rundef.js 1371 2018-04-18
Flow\Flow.runs\synth_1\runme.bat 268 2018-04-18
Flow\Flow.runs\synth_1\runme.log 16166 2018-04-18
Flow\Flow.runs\synth_1\runme.sh 1240 2018-04-18
Flow\Flow.runs\synth_1\vivado.jou 670 2018-04-18
Flow\Flow.runs\synth_1\vivado.pb 26845 2018-04-18
Flow\Flow.sim\sim_1\behav\compile.bat 248 2018-04-18
Flow\Flow.sim\sim_1\behav\compile.log 410 2018-04-18
Flow\Flow.sim\sim_1\behav\glbl.v 1470 2015-11-18
Flow\Flow.sim\sim_1\behav\modelsim.ini 11648 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\@flow\verilog.prw 419 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\@flow\verilog.psm 13104 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\@flow\_primary.dat 980 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\@flow\_primary.dbs 991 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\@flow\_primary.vhd 1063 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\glbl\verilog.prw 905 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\glbl\verilog.psm 13224 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\glbl\_primary.dat 1333 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\glbl\_primary.dbs 1694 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\glbl\_primary.vhd 351 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\testbench\verilog.prw 632 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\testbench\verilog.psm 9472 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\testbench\_primary.dat 1001 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\testbench\_primary.dbs 2535 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\testbench\_primary.vhd 78 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\_info 1118 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\_vmake 26 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\_info 86 2018-04-18
Flow\Flow.sim\sim_1\behav\simulate.bat 248 2018-04-18
Flow\Flow.sim\sim_1\behav\testbench.udo 284 2018-04-18
Flow\Flow.sim\sim_1\behav\testbench_compile.do 891 2018-04-18
Flow\Flow.sim\sim_1\behav\testbench_simulate.do 553 2018-04-18
Flow\Flow.sim\sim_1\behav\testbench_wave.do 320 2018-04-18
Flow\Flow.sim\sim_1\behav\wave.do 866 2018-04-18
Flow\Flow.sim\sim_1\behav\work\_info 86 2018-04-18
Flow\Flow.sim\sim_1\behav\xelab.pb 2088 2018-04-18
Flow\Flow.srcs\sim_1\new\testbench.v 1951 2018-04-18
Flow\Flow.srcs\sources_1\imports\new\Flow.v 2254 2018-04-17
Flow\Flow.srcs\sources_1\new\Flow.v 2375 2018-04-18
Flow\Flow.xpr 5437 2018-04-18
Flow\testbench_behav.wcfg 2940 2018-04-18
Flow\testbench_behav1.wcfg 1511 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\@flow 0 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\glbl 0 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\testbench 0 2018-04-18
Flow\Flow.sim\sim_1\behav\msim\xil_defaultlib\_temp 0 2018-04-18
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Flow\Flow.sim\sim_1\behav\msim 0 2018-04-18
Flow\Flow.sim\sim_1\behav\work 0 2018-04-18
Flow\Flow.srcs\sources_1\imports\new 0 2018-04-17
Flow\Flow.cache\compile_simlib\activehdl 0 2018-04-18
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Flow\Flow.cache\compile_simlib\modelsim 0 2018-04-18
Flow\Flow.cache\compile_simlib\questa 0 2018-04-18
Flow\Flow.cache\compile_simlib\riviera 0 2018-04-18
Flow\Flow.cache\compile_simlib\vcs 0 2018-04-18
Flow\Flow.runs\synth_1\.Xil 0 2018-04-18
Flow\Flow.sim\sim_1\behav 0 2018-04-18
Flow\Flow.srcs\sim_1\new 0 2018-04-17
Flow\Flow.srcs\sources_1\imports 0 2018-04-17
Flow\Flow.srcs\sources_1\new 0 2018-04-18
Flow\Flow.cache\compile_simlib 0 2018-04-18
Flow\Flow.cache\wt 0 2018-04-18
Flow\Flow.ip_user_files\ipstatic 0 2018-04-17
Flow\Flow.runs\.jobs 0 2018-04-18
Flow\Flow.runs\synth_1 0 2018-04-18
Flow\Flow.sim\sim_1 0 2018-04-18
Flow\Flow.srcs\sim_1 0 2018-04-17
Flow\Flow.srcs\sources_1 0 2018-04-17
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