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altera_avalon_pwm

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-18
  • Size : 42kb
  • Downloaded :0次
  • Author :鱼*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
PWM module design based on nios2, compatible with Avalon bus structure
Packet file list
(Preview for download)
FilenameSizeUpdate
altera_avalon_pwm 0 2018-04-11
altera_avalon_pwm\HAL 0 2018-04-11
altera_avalon_pwm\HAL\inc 0 2018-04-11
altera_avalon_pwm\HAL\inc\altera_avalon_pwm.h 2800 2007-05-20
altera_avalon_pwm\HAL\src 0 2018-04-11
altera_avalon_pwm\HAL\src\altera_avalon_pwm.c 3416 2007-05-20
altera_avalon_pwm\HAL\src\component.mk 141 2007-05-20
altera_avalon_pwm\cb_generator.pl 31277 2007-05-20
altera_avalon_pwm\class.ptf 20861 2007-05-20
altera_avalon_pwm\hdl 0 2018-04-11
altera_avalon_pwm\hdl\pwm_avalon_interface.v 1626 2007-05-20
altera_avalon_pwm\hdl\pwm_register_file.v 2583 2007-05-20
altera_avalon_pwm\hdl\pwm_task_logic.v 990 2007-05-20
altera_avalon_pwm\inc 0 2018-04-11
altera_avalon_pwm\inc\altera_avalon_pwm_regs.h 3334 2007-05-20
altera_avalon_pwm\pwm_test 0 2018-04-11
altera_avalon_pwm\pwm_test\pwm_test.c 4702 2007-05-20
altera_avalon_pwm\pwm核说明.txt 751 2018-04-11
altera_avalon_pwm\sim 0 2018-04-11
altera_avalon_pwm\sim\cmd.bat 270 2018-04-11
altera_avalon_pwm\sim\parameters.v 335 2018-04-11
altera_avalon_pwm\sim\pwm.rc 1921 2018-04-11
altera_avalon_pwm\sim\run.f 96 2018-04-11
altera_avalon_pwm\sim\run.f.bak 86 2018-04-11
altera_avalon_pwm\sim\sim.do 86 2018-04-11
altera_avalon_pwm\sim\sim.do.bak 88 2018-01-16
altera_avalon_pwm\sim\sim.log 1023 2018-04-11
altera_avalon_pwm\sim\sim_tim1_task.v 1127 2018-04-11
altera_avalon_pwm\sim\sim_tim1_task.v.bak 1123 2018-04-11
altera_avalon_pwm\sim\test_pwm.fsdb 332422 2018-04-11
altera_avalon_pwm\sim\test_pwm.v 2485 2018-04-11
altera_avalon_pwm\sim\test_pwm.v.bak 2487 2018-04-11
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