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FP_adder

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-21
  • Size : 11kb
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  • Author ：lik***
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Introduction - If you have any usage issues, please Google them yourself
32 bit floating point adder with testbench
Packet file list
(Preview for download)
FilenameSizeUpdate
FP_adder\.gitignore 35 2017-12-10
FP_adder\adder.v 6920 2017-12-10
FP_adder\c_test\test 8496 2017-12-10
FP_adder\c_test\test.cpp 237 2017-12-10
FP_adder\file_reader_a.v 7932 2017-12-10
FP_adder\file_reader_b.v 7932 2017-12-10
FP_adder\file_writer.v 6825 2017-12-10
FP_adder\run_test.py 6148 2017-12-10
FP_adder\stim_z 0 2017-12-10
FP_adder\test_bench.v 1219 2017-12-10
FP_adder\test_bench_tb.v 316 2017-12-10
FP_adder\c_test 0 2017-12-10
FP_adder 0 2017-12-10
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