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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-04-28
  • Size : 17kb
  • Downloaded :0次
  • Author :歌不***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Realization of AD7606 data acquisition
Packet file list
(Preview for download)
FilenameSizeUpdate
rtl\ad706_test.v 4575 2018-04-20
rtl\ad706_test.v.bak 5104 2018-04-19
rtl\ad7606.v 6509 2018-04-20
rtl\ad7606.v.bak 6511 2018-04-20
rtl\bcd.v 4710 2018-04-20
rtl\bcd.v.bak 4691 2018-04-20
rtl\clkdiv.v 859 2018-04-20
rtl\clkdiv.v.bak 771 2018-04-20
rtl\uart.v 11281 2018-04-20
rtl\uart.v.bak 11221 2018-04-20
rtl\uarttx.v 3858 2018-04-20
rtl\uarttx.v.bak 3770 2018-04-20
rtl\volt_cal.v 7792 2018-04-20
rtl\volt_cal.v.bak 7732 2018-04-20
rtl 0 2018-04-20
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