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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-05-15
  • Size : 433kb
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  • Author :闭家***
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Introduction - If you have any usage issues, please Google them yourself
1, must do: design and implement a 8 * 8 dot matrix scanning controller, stable display of a number or letter on the dot matrix, the color is red and green. 2, choose to do: display characters with 8 x 8 dot matrix, display one character each time, switch once a second, display the contents of "B", "U", "P", "T" and the first letter of the name. For example, Zhang San shows the contents of "B", "U", "P", "T", "Z" and "S".
Packet file list
(Preview for download)
FilenameSizeUpdate
db 0 2018-05-15
db\logic_util_heursitic.dat 6424 2018-05-15
db\prev_cmp_U4.qmsg 71335 2018-05-15
db\U4.(0).cnf.cdb 1704 2018-05-15
db\U4.(0).cnf.hdb 1140 2018-05-15
db\U4.(1).cnf.cdb 2423 2018-05-15
db\U4.(1).cnf.hdb 921 2018-05-15
db\U4.(2).cnf.cdb 1468 2018-05-15
db\U4.(2).cnf.hdb 865 2018-05-15
db\U4.(3).cnf.cdb 1137 2018-05-15
db\U4.(3).cnf.hdb 813 2018-05-15
db\U4.(4).cnf.cdb 5272 2018-05-15
db\U4.(4).cnf.hdb 1981 2018-05-15
db\U4.asm.qmsg 2495 2018-05-15
db\U4.asm.rdb 1385 2018-05-15
db\U4.asm_labs.ddb 2799 2018-05-15
db\U4.cbx.xml 84 2018-05-15
db\U4.cmp.cdb 25844 2018-05-15
db\U4.cmp.hdb 13117 2018-05-15
db\U4.cmp.idb 8816 2018-05-15
db\U4.cmp.kpt 216 2018-05-15
db\U4.cmp.logdb 4 2018-05-15
db\U4.cmp.rdb 14476 2018-05-15
db\U4.cmp0.ddb 52916 2018-05-15
db\U4.db_info 154 2018-05-15
db\U4.eda.qmsg 2470 2018-05-15
db\U4.fit.qmsg 32922 2018-05-15
db\U4.hier_info 5278 2018-05-15
db\U4.hif 570 2018-05-15
db\U4.ipinfo 177 2018-05-15
db\U4.lpc.html 1161 2018-05-15
db\U4.lpc.rdb 506 2018-05-15
db\U4.lpc.txt 2120 2018-05-15
db\U4.map.cdb 8934 2018-05-15
db\U4.map.hdb 12553 2018-05-15
db\U4.map.logdb 4 2018-05-15
db\U4.map.qmsg 19604 2018-05-15
db\U4.map.rdb 1241 2018-05-15
db\U4.pplq.rdb 246 2018-05-15
db\U4.pre_map.hdb 12039 2018-05-15
db\U4.pti_db_list.ddb 191 2018-05-15
db\U4.root_partition.map.reg_db.cdb 353 2018-05-15
db\U4.routing.rdb 2027 2018-05-15
db\U4.rtlv.hdb 11822 2018-05-15
db\U4.rtlv_sg.cdb 8398 2018-05-15
db\U4.rtlv_sg_swap.cdb 934 2018-05-15
db\U4.sgdiff.cdb 8047 2018-05-15
db\U4.sgdiff.hdb 11520 2018-05-15
db\U4.sld_design_entry.sci 216 2018-05-15
db\U4.sld_design_entry_dsc.sci 216 2018-05-15
db\U4.smart_action.txt 6 2018-05-15
db\U4.sta.qmsg 11864 2018-05-15
db\U4.sta.rdb 14969 2018-05-15
db\U4.sta_cmp.5_slow.tdb 23590 2018-05-15
db\U4.syn_hier_info 0 2018-05-15
db\U4.tis_db_list.ddb 191 2018-05-15
db\U4.vpr.ammdb 403 2018-05-15
incremental_db 0 2018-05-15
incremental_db\compiled_partitions 0 2018-05-15
incremental_db\compiled_partitions\U4.db_info 154 2018-05-15
incremental_db\compiled_partitions\U4.root_partition.map.kpt 998 2018-05-15
incremental_db\README 653 2018-05-15
output_files 0 2018-05-15
output_files\U4.asm.rpt 7053 2018-05-15
output_files\U4.done 26 2018-05-15
output_files\U4.eda.rpt 5708 2018-05-15
output_files\U4.fit.rpt 79819 2018-05-15
output_files\U4.fit.smsg 370 2018-05-15
output_files\U4.fit.summary 373 2018-05-15
output_files\U4.flow.rpt 7547 2018-05-15
output_files\U4.jdi 222 2018-05-15
output_files\U4.map.rpt 27602 2018-05-15
output_files\U4.map.summary 308 2018-05-15
output_files\U4.pin 19995 2018-05-15
output_files\U4.pof 27336 2018-05-15
output_files\U4.sta.rpt 130563 2018-05-15
output_files\U4.sta.summary 1081 2018-05-15
simulation 0 2018-05-15
simulation\modelsim 0 2018-05-15
simulation\modelsim\U4.sft 43 2018-05-15
simulation\modelsim\U4.vo 137716 2018-05-15
simulation\modelsim\U4_modelsim.xrf 8055 2018-05-15
simulation\qsim 0 2018-05-15
simulation\qsim\transcript 955 2018-05-15
simulation\qsim\U4.do 320 2018-05-15
simulation\qsim\U4.msim.vcd 23719 2018-05-15
simulation\qsim\U4.msim.vwf 138926 2018-05-15
simulation\qsim\U4.sim.vwf 23645 2018-05-15
simulation\qsim\U4.vo 99440 2018-05-15
simulation\qsim\U4.vt 14005 2018-05-15
simulation\qsim\vsim.wlf 73728 2018-05-15
simulation\qsim\work 0 2018-05-15
simulation\qsim\work\@u4 0 2018-05-15
simulation\qsim\work\@u4\_primary.dat 58171 2018-05-15
simulation\qsim\work\@u4\_primary.dbs 64120 2018-05-15
simulation\qsim\work\@u4\_primary.vhd 290 2018-05-15
simulation\qsim\work\@u4\verilog.prw 229 2018-05-15
simulation\qsim\work\@u4\verilog.psm 283144 2018-05-15
simulation\qsim\work\@u4_vlg_check_tst 0 2018-05-15
simulation\qsim\work\@u4_vlg_check_tst\_primary.dat 7672 2018-05-15
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