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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-06-06
  • Size : 7kb
  • Downloaded :0次
  • Author :小*****
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Introduction - If you have any usage issues, please Google them yourself
The implementation of the serial port and transceiver, can run stable
Packet file list
(Preview for download)
FilenameSizeUpdate
rtl\clkdiv.v 826 2017-02-03
rtl\clkdiv.v.bak 644 2015-11-04
rtl\testdata.v 1636 2015-11-04
rtl\testdata.v.bak 908 2015-11-04
rtl\uartctrl.v 4838 2016-02-25
rtl\uartrx.v 4120 2017-02-03
rtl\uartrx.v.bak 3480 2015-11-04
rtl\uarttx.v 3726 2017-02-04
rtl\uart_test.v 1675 2017-02-04
rtl\uart_test.v.bak 341 2015-11-04
rtl 0 2018-05-11
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