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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2018-06-06
- Size : 21.94mb
- Downloaded ：1次
- Author ：喵****
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Introduction - If you have any usage issues, please Google them yourself
This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.
Packet file list
(Preview for download)
| Filename | Size | Update |
|---|---|---|
| XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之应用篇_中文版教程.pdf | 792873 | 2015-10-27 |
| XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之综合篇_中文版教程.pdf | 2710017 | 2015-10-27 |
| XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之设计篇_中文版教程.pdf | 4930108 | 2015-10-27 |
| XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之高富帅篇_中文版教程.pdf | 621371 | 2015-10-27 |
| XILINX平台DDR3设计教程\xilinx平台DDR3设计教程之仿真篇_中文版教程.pdf | 21864666 | 2013-12-01 |
| XILINX平台DDR3设计教程 | 0 | 2017-09-29 |
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