This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.

Filename	Size	Update
XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之应用篇_中文版教程.pdf	792873	2015-10-27
XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之综合篇_中文版教程.pdf	2710017	2015-10-27
XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之设计篇_中文版教程.pdf	4930108	2015-10-27
XILINX平台DDR3设计教程\eetop.cn_xilinx平台DDR3设计教程之高富帅篇_中文版教程.pdf	621371	2015-10-27
XILINX平台DDR3设计教程\xilinx平台DDR3设计教程之仿真篇_中文版教程.pdf	21864666	2013-12-01
XILINX平台DDR3设计教程	0	2017-09-29

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