This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code

Packet : 69491713ehernetipcore.rar filelist
以太网IP core\eth_shiftreg.v
以太网IP core\eth_sync_clk1_clk2.v
以太网IP core\eth_top.v
以太网IP core\eth_transmitcontrol.v
以太网IP core\eth_txcounters.v
以太网IP core\eth_txethmac.v
以太网IP core\eth_txstatem.v
以太网IP core\eth_wishbonedma.v
以太网IP core\timescale.v
以太网IP core\eth_clockgen.v
以太网IP core\eth_crc.v
以太网IP core\eth_defines.v
以太网IP core\eth_maccontrol.v
以太网IP core\eth_macstatus.v
以太网IP core\eth_miim.v
以太网IP core\eth_outputcontrol.v
以太网IP core\eth_random.v
以太网IP core\eth_receivecontrol.v
以太网IP core\eth_register.v
以太网IP core\eth_registers.v
以太网IP core\eth_rxcounters.v
以太网IP core\eth_rxethmac.v
以太网IP core\eth_rxstatem.v
以太网IP core\tb_eth_top.v
以太网IP core

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