SRIO_DSP_X1 fpga and dsp communation with srio

SRIO_DSP_X1

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Category : VHDL-FPGA-Verilog
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Update : 2018-08-09
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fpga and dsp communation with srio

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Filename	Size	Update
ForDownload	0	2016-05-14
ForDownload\srio_example_top_srio_gen2_0.bin	3825788	2016-03-29
ForDownload\srio_example_top_srio_gen2_0.bit	3825913	2016-03-29
ForDownload\SRIO_FPGA.out	3314376	2016-04-28
FPGA	0	2016-04-28
FPGA\srio_gen2_0_example	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\constrs_1	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\constrs_1\imports	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\constrs_1\imports\example_design	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\constrs_1\imports\example_design\srio_gen2_0.xdc	2786	2016-03-29
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sim_1	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sim_1\imports	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sim_1\imports\example_design	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sim_1\imports\example_design\instruction_list.vh	9246	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sim_1\imports\example_design\maintenance_list.vh	34587	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sim_1\imports\example_design\srio_sim.v	9478	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\instruction_list.vh	9246	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\maintenance_list.vh	34587	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\srio_example_top_srio_gen2_0.v	40081	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\srio_quick_start_srio_gen2_0.v	22080	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\srio_report.v	6163	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\srio_request_gen_srio_gen2_0.v	19250	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\srio_response_gen_srio_gen2_0.v	18170	2016-03-25
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\imports\example_design\srio_statistics_srio_gen2_0.v	17489	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\blk_mem_gen_v8_2	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\blk_mem_gen_v8_2\hdl	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\blk_mem_gen_v8_2\hdl\blk_mem_gen_v8_2.vhd	20447	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\blk_mem_gen_v8_2\hdl\blk_mem_gen_v8_2_vhsyn_rfs.vhd	14794011	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\blk_mem_gen_v8_2\simulation	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\blk_mem_gen_v8_2\simulation\blk_mem_gen_v8_2.v	163494	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\doc	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\doc\srio_gen2_v4_0_changelog.txt	4541	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\hdl	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\hdl\fifo_generator_v12_0.vhd	90327	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\hdl\fifo_generator_v12_0_rfs.v	593425	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\hdl\fifo_generator_v12_0_rfs.vhd	1368841	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\hdl\fifo_generator_v12_0_vhsyn_rfs.vhd	2215703	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\simulation	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\fifo_generator_v12_0\simulation\fifo_generator_vlog_beh.v	396623	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0.dcp	2469703	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0.veo	12150	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0.xci	24189	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0.xml	515264	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0_core.xdc	505	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0_funcsim.v	7017357	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0_funcsim.vhdl	8394747	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0_stub.v	7319	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_0_stub.vhdl	7116	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_v4_0	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_v4_0\hdl	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_v4_0\hdl\srio_gen2_v4_0_rfs.v	2343903	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_v4_0\hdl\srio_gen2_v4_0_rfs.vhd	290864	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth	0	2016-04-28
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\cfg_fabric_srio_gen2_0.v	26945	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\gt_wrapper_srio_gen2_0.v	22489	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0.v	15670	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_a7_gtpe2_common.v	9551	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_block.v	51976	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtp_GT.v	52962	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtp_multi_gt.v	18156	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtpe2_gtrxreset_seq.v	9236	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtpe2_init.v	29575	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtpe2_rx_startup_fsm.v	29872	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtpe2_rxpmarst_seq.v	9849	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtpe2_sync_block.v	4560	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_gtpe2_tx_startup_fsm.v	21607	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_ooc.xdc	425	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_srio_clk.v	4642	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_srio_rst.v	9350	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gen2_0_support.v	20473	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.srcs\sources_1\ip\srio_gen2_0\synth\srio_gt_wrapper_srio_gen2_0_a7_1x.v	19668	2016-03-23
FPGA\srio_gen2_0_example\srio_gen2_0_example.xpr	10561	2016-03-29
说明.txt	66	2016-05-14

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