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eetop.cn_ISCAS89(verilog)
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Category :
VHDL-FPGA-Verilog
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Update : 2018-08-26
Size : 1010kb
Downloaded :0次
Author :
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Introduction - If you have any usage issues, please Google them yourself
Reedit
iscas89 benchmark, written in verilog language, can be used to generate test pattern
Packet file list
(Preview for download)
Filename
Size
Update
verilog\s1238.v
18927
1997-08-12
verilog\s13207.v
328755
1997-08-12
verilog\s1423.v
25622
1997-08-12
verilog\s1488.v
28410
1997-08-12
verilog\s1494.v
28274
1997-08-12
verilog\s15850.v
399114
1997-08-12
verilog\s27.v
762
1997-08-12
verilog\s298.v
4740
1997-08-12
verilog\s344.v
8880
1997-08-12
verilog\s349.v
8966
1997-08-12
verilog\s35932.v
825679
1997-08-12
verilog\s382.v
9871
1997-08-12
verilog\s38417.v
999483
1997-08-12
verilog\s38584.v
883843
1997-08-12
verilog\s386.v
7269
1997-08-12
verilog\s400.v
10212
1997-08-12
verilog\s420.v
8957
1997-08-12
verilog\s444.v
7657
1997-08-12
verilog\s510.v
9655
1997-08-12
verilog\s526.v
7840
1997-08-12
verilog\s526n.v
7869
1997-08-12
verilog\s5378.v
137277
1997-08-12
verilog\s641.v
14582
1997-08-12
verilog\s713.v
15377
1997-08-12
verilog\s820.v
11479
1997-08-12
verilog\s832.v
11467
1997-08-12
verilog\s838.v
18622
1997-08-12
verilog\s9234.v
217860
1997-08-12
verilog\s953.v
18772
1997-08-12
verilog\s1196.v
19439
1997-08-12
verilog
0
2007-09-17
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