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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-09-14
  • Size : 5kb
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  • Author :午*****
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Introduction - If you have any usage issues, please Google them yourself
Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb filter unit, is very helpful for beginners.
Packet file list
(Preview for download)
FilenameSizeUpdate
CIC\addra_out.v 812 2015-07-14
CIC\comb.v 983 2015-07-06
CIC\cos.coe 1027 2015-07-06
CIC\data.v 682 2015-07-14
CIC\decimate.v 964 2015-07-06
CIC\integrated.v 1064 2015-07-14
CIC\sin.coe 1030 2015-07-06
CIC\square.coe 16444 2015-06-30
CIC\top.v 1501 2015-07-14
CIC\triangular.coe 18806 2015-06-30
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